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13

This circuit is used to initialize the microcomputer when it incorporates an AC adaptor or PoE HUB.

When the AC Adaptor is inserted into the unit, then the voltage is shifted by IC401 and power is supplied to the DSP.
The set starts to operate when VCC goes up to 3.2 V in the circuit voltage diagram.

Main system clock (13.824MHz) is generated from X100, and Oscillation circuit consists of X100 and IC101.
This clock is used for basic clock of IC101's all internal clock.
This clock is supplied to IC300  via BCLK output of IC101.
X201 is used by IC100 during its boot sequence.

12MHz is generated from X101, and Oscillation circuit consists of X201 and IC101.
This clock is used for USB Interface.

25MHz is generated from X200, and Oscillation circuit consists of X200 and IC200.
This clock is used for Ethernet Interface. And it is used for basic clock of IC200's all internal clock.

AC ADAPTOR

PoE HUB

IC201

IC103

VCC (3.2V)

RESET (IC101)

IC401

VCC(3.2V)

1.8V at IC 101

RESET (IC101)

BCLK (IC101)

IC101

X100

X201

13.824MHz

12MHz

(BCLK) 13.824MHz 

TO IC300

IC200

X200

25MHz

14

TGP600 have been using the PHY-IC(IC201) in the exchange of signals with the ETHER
PHY-IC connects a link layer device (often called MAC as an abbreviation for media access control) to a physical medium an
copper cable.
A PHY-IC includes a Physical Coding Sublayer (PCS) and a Physical Medium Dependent (PMD) layer.
The PCS encodes and decodes the data that is transmitted and received.
The purpose of the encoding is to make it easier for the receiver to recover the signal.

If there is communication data toward the TGP600 from ETHER, then RXDV becomes HI, signal is transmitted to the IC101 through
RXD0-RXD3.
RXD0-RXD3 are synchronized to RXCK. 

If there is a communication data toward the HUB from TGP600 then  the TXEN  is set to HI,issue a signal to IC200 through TXD0-
TXD3. 
TXD0-TXD3 are synchronized to TXCK. 

IC101(Main)

IC201(PHY-IC)

T200

JK201

MII_TXEN

MII_TXD0

TXD3

MII_RXDV,RXCK

PHY_RST

MDC

MDIO

MII_CRS,MII_COL,
MII_RXER

TX+/Tx-

RX+/Rx-

MDI+0
/MDI-0

MDI+1
/MDI-1

HUB

TXCK

MII_RXD0

RXD3

15

BAT +

VBAT

BAT -

CHG

 -

CH

G

 +

Key (26

)

(Tri

an

g

le

 Matri

x

)

LCD_Back

light

Key_Bac

klight

MIC

RE

CEIV

ER

HEADSET

JACK

SPE

AKER

3v

X1

13.824MHz

4v

ANT

KB

IO1

8

MIP

MIN

HSSPOUT

P

LO

UT

H

SMI

P

HEAD

SET

_DET

SPOUT

P

SPOUT

N

KE

Y

_

B

L

LCD_BL1

LCD_BL2

DOUBOUT

C

HG_CT

RL

CHG_D

ET

BAT

C

HG_CU

R

S

e

rial Fl

ash Mem

ory

64MBit

Win

bond

1.8”

TFT  Color

 LCD

12

8x160

dot 

(Tr

u

ly /D

r-

IC

 : H

X

83

53)

RF

QSPI

SPI

RF I/

F

Uar

t

Uar

t I/F

J

T

AG I/F

Ni-MH

JT

A

G

BE

LL_LED (RED)

BELL_RED

IC1

DCX81

LED_SINK

Charge 

Circuit

Circuit

Q501

LED501    507

LED530

16

The circuit mainly consists of DSP part as shown in the block diagram.

• Battery Low, Power down detect circuit
• Ringer Generation
• Interface circuit

Speaker, Mic, LED, Key, LCD, Flash Memory

• RF  part

PLL Oscilator, Detector, Compress/Expander, Amplifier for reception/trnsmission

All setting data is stored.
ex: ID code, user setting (Phonebook, program data)