DOWNLOAD Panasonic KX-NSX1000 / KX-NSX2000 (serv.man2) Service Manual ↓ Size: 9.94 MB | Pages: 127 in PDF or view online for FREE

Model
KX-NSX1000 KX-NSX2000 (serv.man2)
Pages
127
Size
9.94 MB
Type
PDF
Document
Service Manual
Brand
Device
PBX / BUSINESS COMMUNICATION SERVER
File
kx-nsx1000-kx-nsx2000-sm2.pdf
Date
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Panasonic KX-NSX1000 / KX-NSX2000 (serv.man2) Service Manual ▷ View online

77
KX-NSX1000/KX-NSX2000
AB16
DSP#1_A[5]
O
DSP#1 Address Bus Bit5
AB17
DSP#1_A[2]
O
DSP#1 Address Bus Bit2
AB18
DSP#1_nWE
O
DSP#1 Write Enable signal
AB19
DSP#1_D[14]
I/O
DSP#1 Data Bus Bit14
AB20
DSP#1_D[10]
I/O
DSP#1 Data Bus Bit10
AB21
DSP#1_D[7]
I/O
DSP#1 Data Bus Bit7
AB22
DSP#1_D[5]
I/O
DSP#1 Data Bus Bit5
B1
SO/SIO1
I
MOH Flash Data Input
B2
-
GND
B3
INITIALIZE_SW
O
INITIALIZE SW Input
B4
FPGA_STS_LED_RED
O
Drive signal for STATUS Red LED 
B5
-
GND
B6
FAN_ALM#2_FPGA
I
FAN#2 Alarm Input signal 
B7
FPGA_DEVSLP_SSD#2
O
Depp sleep control signal(DEVSLP) for SSD#2
B8
-
GND
B9
BUF_PCIE_RSTn_FPGA
I
PCI Express Reset Input
B10
DSP#2_TDM0_RX_DSP
I
DSP#2 TDM Bus 0 Data input
B11
-
GND
B12
DSP#2_B_CLK
O
DSP#2 B_CLK signal output
B13
DSP#2_nCS_DSP1
O
DSP#2/DSP1 ship select output
B14
-
GND
B15
DSP_D[1]
I/O
DSP#2, #3  Data Bus Bit1
B16
DSP_D[5]
I/O
DSP#2, #3  Data Bus Bit5
B17
-
GND
B18
DSP_D[10]
I/O
DSP#2, #3  Data Bus Bit10
B19
DSP_nBE1
O
DSP#2, #3  Upper Byte Enable
B20
DSP_nBE0
O
DSP#2, #3  Lower Byte Enable
B21
DSP_nWE
O
DSP#2, #3  Write Enable
B22
DSP_nRD
O
DSP#2, #3  Read Enable
C1
nWP/SIO2
O
MOH Flash Write protect siganal
C2
SCLK
O
MOH Flash SCLK signal
C3
FPGA_BAT_LED
O
Drive signal for Batery Alarm LED
C4
FPGA_MS_LED_GREEN
O
Drive signal for System mode Green LED
C5
CEX_DEBUG_LED1
O
Debug LED
C6
AC_ALMn_FPGA
I
AC_ALM signal input
C7
DSP#2_CARD_ID[0]
I
DSP#2 CARD ID Bit0 Input
C8
DSP#2_CARD_ID[3]
I
DSP#2 CARD ID Bit3 Input
C9
DSP#2_CARD_ID[5]
I
DSP#2 CARD ID Bit5 Input
C10
DSP#2_TDM0_FS_DSP
O
DSP#1 TDM Bus 0 FS signal output
C11
DSP#2_DSP_nRST
O
DSP#2 DSP reset signal
C12
DSP#2_nRST_PORT_PHY
O
DSP#2 PHY reset signal
C13
DSP#2_nINT_DSP0
I
Interrupt signal from DSP#2/DSP0
C14
DSP#2_TDM1_RX_DSP
I/O
DSP#2 TDM Bus 1 Data input
C15
DSP_D[2]
I/O
DSP#2, #3  Data Bus Bit3
C16
DSP_D[6]
I/O
DSP#2, #3  Data Bus Bit6
C17
DSP_D[11]
I/O
DSP#2, #3  Data Bus Bit8
C18
DSP_D[8]
I/O
DSP#2, #3  Data Bus Bit11
C19
DSP_A[3]
O
DSP#2, #3  Address Bus Bit3
C20
DSP_A[2]
O
DSP#2, #3  Address Bus Bit2
C21
-
GND
C22
DSP_A[1]
O
DSP#2, #3  Address Bus Bit1
D1
SI/IO0
I/O
CONFIG Flash Data Input/Output
D2
nCE
I
GND
D3
DCLK
I/O
CONFIG Flash clock output
D4
FPGA_MS_LED_RED
O
Drive signal for System mode Red LED
D5
O
Test pin for debug
D6
DC_ALMn_FPGA
I
DC_ALM signal input
D7
DSP#2_CARD_ID[1]
I
DSP#2 CARD ID Bit1 Input
D8
DSP#2_CARD_ID[4]
I
DSP#2 CARD ID Bit4 Input
D9
DSP#2_CARD_ID[6]
I
DSP#2 CARD ID Bit6 Input
D10
I/O
OPEN
D11
I/O
OPEN
D12
I/O
OPEN
D13
I/O
OPEN
D14
DSP#2_nINT_DSP1
I
Interrupt signal from DSP#2/DSP1
D15
DSP_D[3]
I/O
DSP#2, #3  Data Bus Bit3
D16
I/O
OPEN
Pin No.
Signal Name
I/O
Function
78
KX-NSX1000/KX-NSX2000
D17
I/O
OPEN
D18
-
GND
D19
DSP_A[7]
O
DSP#2, #3  Address Bus Bit7
D20
DSP_A[6]
O
DSP#2, #3  Address Bus Bit6
D21
DSP_A[5]
O
DSP#2, #3  Address Bus Bit5
D22
DSP_A[4]
O
DSP#2, #3  Address Bus Bit4
E1
-
GND
E2
-
GND
E3
TDO
O
Connect to USB-Blaster connecor
E4
TCK
I
Connect to USB-Blaster connecor
E5
O
Test pin for debug
E6
BAT_ARMn_FPGA
O
Battery Alarm signal input from COM Express module
E7
-
GND
E8
I/O
OPEN
E9
-
Connect to 3.3V
E10
-
Connect to 3.3V
E11
-
Connect to 3.3V
E12
-
Connect to 3.3V
E13
-
Connect to 3.3V
E14
-
Connect to 3.3V
E15
-
Connect to 3.3V
E16
-
Connect to 3.3V
E17
I/O
OPEN
E18
-
Connect to 3.3V
E19
-
GND
E20
DSP#3_TDM0_CK_DSP
O
DSP#3 TDM Bus 0 clock
E21
DSP#3_TDM0_RX_DSP
I
DSP#3 TDM Bus 0 Input
E22
DSP#3_TDM0_FS_DSP
O
DSP#1 TDM Bus 1 Frame Sync signal output
F1
GXB_TX3N
O
OPEN
F2
GXB_TX3P
O
OPEN
F3
-
GND
F4
-
Connect to 2.5V
F5
TDI
I
Connect to USB-Blaster connecor
F6
I/O
OPEN
F7
-
Connect to 1.2V
F8
I/O
OPEN
F9
-
GND
F10
-
Connect to 3.3V
F11
-
GND
F12
I/O
OPEN
F13
-
GND
F14
-
Connect to 3.3V
F15
-
GND
F16
I/O
OPEN
F17
I/O
OPEN
F18
I/O
OPEN
F19
-
Connect to 2.5V
F20
DSP#3_CARDID_nOE
O
DSP#3 CARD ID Output Enable
F21
-
GND
F22
DSP#3_TDM0_DX_DSP
O
DSP#3 TDM Bus 0 Data Output
G1
-
GND
G2
-
GND
G3
-
Connect to 1.2V
G4
-
Connect to 3.3V
G5
TMS
I
Connect to USB-Blaster connecor
G6
I/O
OPEN
G7
I/O
OPEN
G8
I/O
OPEN
G9
-
Connect to 1.2V
G10
I/O
OPEN
G11
I/O
OPEN
G12
I/O
OPEN
G13
-
Connect to 1.2V
G14
I/O
OPEN
G15
I/O
OPEN
G16
I/O
OPEN
G17
I/O
OPEN
Pin No.
Signal Name
I/O
Function
79
KX-NSX1000/KX-NSX2000
G18
I/O
OPEN
G19
DSP#3_nCS_DSP0
O
DSP#3/DSP0 chip select
G20
DSP#3_nRST_PORT_PHY
O
DSP#3 PHY reset signal
G21
DSP#3_DSP_nRST
O
DSP#3 DSP reset signal
G22
DSP#3_B_CLK
O
DSP#1 B_CLK clock signal
H1
GXB_RX3N
I
GND with other pin by register
H2
GXB_RX3P
I
GND with other pin by register
H3
-
Connect to 2.5V
H4
nCONFIG
I
FPGA configuration trig input
H5
-
GND
H6
-
Connect to 1.2V
H7
I/O
OPEN
H8
I/O
OPEN
H9
I/O
OPEN
H10
-
Connect to 2.5V
H11
-
GND
H12
I/O
OPEN
H13
I/O
OPEN
H14
I/O
OPEN
H15
I/O
OPEN
H16
I/O
OPEN
H17
I/O
OPEN
H18
-
GND
H19
-
Connect to 3.3V
H20
DSP#3_nCS_DSP1
O
DSP#3/DSP1 chip select
H21
DSP#3_TDM1_RX_DSP
I
DSP#3 TDM Bus 1 Data Input
H22
DSP#3_TDM1_DX_DSP
O
DSP#3 TDM Bus 1 Data Output
J1
-
GND
J2
-
GND
J3
-
Connect to 2.5V
J4
nCS
O
FPGA  configuration rom chip select
J5
-
Connect to 1.2V
J6
-
GND
J7
-
Connect to 1.2V
J8
-
GND
J9
-
Connect to 1.2V
J10
I
GND
J11
-
Connect to 1.2V
J12
I/O
OPEN
J13
I/O
OPEN
J14
I/O
OPEN
J15
I/O
OPEN
J16
I/O
OPEN
J17
-
Connect to 1.2V
J18
-
Connect to 3.3V
J19
DSP#3_CARD_ID[1]
I
DSP#3 CARD ID Bit1
J20
DSP#3_CARD_ID[0]
I
DSP#3 CARD ID Bit0
J21
DSP#3_nINT_DSP1
I
Interrupt signal from DSP#3/DSP1
J22
DSP#3_nINT_DSP0
I
Interrupt signal from DSP#3/DSP0
K1
GXB_TX2N
O
OPEN
K2
GXB_TX2P
O
OPEN
K3
-
Connect to 1.2V
K4
SO/IO1
I/O
FPGA configuration rom data Input/Output
K5
-
GND
K6
-
Connect to 1.2V
K7
-
GND
K8
-
Connect to 1.2V
K9
-
GND
K10
I
GND
K11
-
GND
K12
I/O
OPEN
K13
I/O
OPEN
K14
I/O
OPEN
K15
-
GND
K16
-
Connect to 1.2V
K17
I/O
OPEN
K18
-
Connect to 3.3V
Pin No.
Signal Name
I/O
Function
80
KX-NSX1000/KX-NSX2000
K19
DSP#3_CARD_ID[4]
I
DSP#3 CARD ID Bit4
K20
DSP#3_CARD_ID[3]
I
DSP#3 CARD ID Bit3
K21
-
GND
K22
DSP#3_CARD_ID[2]
I
DSP#3 CARD ID Bit2
L1
-
GND
L2
-
GND
L3
-
Connect to 1.2V
L4
-
Connect to 2.5V
L5
-
Connect to 1.2V
L6
-
GND
L7
-
Connect to 1.2V
L8
-
GND
L9
-
Connect to 1.2V
L10
-
GND
L11
-
Connect to 1.2V
L12
-
GND
L13
I/O
OPEN
L14
I/O
OPEN
L15
I/O
OPEN
L16
I/O
OPEN
L17
-
Connect to 1.2V
L18
-
GND
L19
DSP#3_CARD_ID[6]
I
DSP#3 CARD ID Bit6
L20
DSP#3_CARD_ID[5]
I
DSP#3 CARD ID Bit5
L21
CLK_16M
I
16.384MHz clock input
L22
CLKIO6
I
GND
M1
GXB_RX2N
I
GND with other pin by register
M2
GXB_RX2P
I
GND with other pin by register
M3
-
GND
M4
-
Connect to 1.2V
M5
-
GND
M6
-
Connect to 1.2V
M7
BUF_PCIE_CLK_P_FPGA
I
PCI Express clock +
M8
REFCLK1P
I
GND with other pin by register
M9
-
GND
M10
-
Connect to 1.2V
M11
I
GND
M12
-
Connect to 1.2V
M13
I/O
OPEN
M14
I/O
OPEN
M15
I/O
OPEN
M16
I/O
OPEN
M17
I/O
OPEN
M18
O
Test pin for debug
M19
O
Test pin for debug
M20
I/O
OPEN
M21
I
GND
M22
I
GND
N1
-
GND
N2
-
GND
N3
-
Connect to 1.2V
N4
-
GND
N5
-
Connect to 1.2V
N6
-
GND
N7
BUF_PCIE_CLK_N_FPGA
I
PCI Express clock -
N8
REFCLK1N
I
GND with other pin by register
N9
-
Connect to 1.2V
N10
-
GND
N11
I
GND
N12
-
Connect to 2.5V
N13
I/O
OPEN
N14
I/O
OPEN
N15
I/O
OPEN
N16
-
Connect to 1.2V
N17
I/O
OPEN
N18
-
Connect to 3.3V
N19
O
Test pin for debug
Pin No.
Signal Name
I/O
Function
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