DOWNLOAD Panasonic KX-NSX1000 / KX-NSX2000 (serv.man2) Service Manual ↓ Size: 9.94 MB | Pages: 127 in PDF or view online for FREE

Model
KX-NSX1000 KX-NSX2000 (serv.man2)
Pages
127
Size
9.94 MB
Type
PDF
Document
Service Manual
Brand
Device
PBX / BUSINESS COMMUNICATION SERVER
File
kx-nsx1000-kx-nsx2000-sm2.pdf
Date
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93
KX-NSX1000/KX-NSX2000
15.1.7.
CN8 (DSP#2 Connector)
Pin No.
Signal name
I/O
Function
2
DSP_CON_No.
O
Fixed to the High Level by mother board
3
n PRESET(DG)
I
Card detection(not used)
4
DG
-
GND
5
DSP#2_CARD_ID[0]
I
DSP#2 DSP CARD TYPE
6
DSP#2_CARD_ID[1]
I
7
DSP#2_CARD_ID[2]
I
8
DSP#2_CARD_ID[3]
I
9
DSP#2_CARD_ID[4]
I
10
DSP#2_CARD_ID[5]
I
11
DSP#2_CARD_ID[6]
I
12
DG
-
GND
13
DSP#2_CARDID_nOE
O
Output Enable for DSP#2 CARD_ID
14
DG
-
GND
15
DSP_D[8]
I/O
DSP#2 & DSP#3 Data bus[8]
16
DSP_D[9]
I/O
DSP#2 & DSP#3 Data bus[9]
17
DSP_D[10]
I/O
DSP#2 & DSP#3 Data bus[10]
18
DSP_D[11]
I/O
DSP#2 & DSP#3 Data bus[11]
19
DG
-
GND
20
DSP_D[12]
I/O
DSP#2 & DSP#3 Data bus[12]
21
DSP_D[13]
I/O
DSP#2 & DSP#3 Data bus[13]
22
DSP_D[14]
I/O
DSP#2 & DSP#3 Data bus[14]
23
DSP_D[15]
I/O
DSP#2 & DSP#3 Data bus[15]
24
DG
-
GND
25
DSP_A[1]
O
DSP#2 & DSP#3 Address bus[1]
26
DSP_A[2]
O
DSP#2 & DSP#3 Address bus[2]
27
DSP_A[3]
O
DSP#2 & DSP#3 Address bus[3]
28
DSP_A[4]
O
DSP#2 & DSP#3 Address bus[4]
29
DG
-
GND
30
DSP_A[5]
O
DSP#2 & DSP#3 Address bus[5]
31
DSP#2_nRST_PORT_PHY
O
DSP#2 PHY Reset
32
DSP#2_nCS_DSP1
O
DSP#2 Card, chip select for DSP1
33
DG
-
GND
34
DSP_A[6]
DSP#2 & DSP#3 Address bus[6]
35
DSP_A[7]
DSP#2 & DSP#3 Address bus[7]
36
DSP#2_nINT_DSP1
I
DSP#2 Card, DSP1  Interrupt Input
37
DSP#2_nINT_DSP0
I
DSP#2 Card, DSP0  Interrupt Input
38
DG
-
GND
39
NC
40
+15V
-
DC Input +15V
41
+15V
-
DC Input +15V
42
NC
43
DG
-
GND
44
DSP#2_TDM1_DX_DSP
O
DSP#2 TDM Transmission data
45
DSP#2_TDM1_RX_DSP
I
DSP#2 TDM Receive data
46
3R3VA_DSP#2
O
DSP#2 3.3VDC Input for Trans
47
(TDM01_CK)
O
Reserve
48
DG
-
GND
49
DSP#2_nCS_DSP0
O
DSP#2 Card, chip select for DSP0
50
DG
-
GND
51
B_CLK_66M
O
DSP#2 Bus clock
52
DG
-
GND
53
DSP_nRD
O
DSP#2 & DSP#3 Read signal
54
DSP_nWE
O
DSP#2 & DSP#3 Write signal
55
DSP_nBE1
O
DSP#2 & DSP#3 Byte Enable[1]
56
DSP_nBE0
O
DSP#2 & DSP#3 Byte Enable[0]
57
DG
-
GND
58
DSP_D[7]
I/O
DSP#2 & DSP#3 Data bus[7]
59
DSP_D[6]
I/O
DSP#2 & DSP#3 Data bus[6]
60
DSP_D[5]
I/O
DSP#2 & DSP#3 Data bus[5]
61
DSP_D[4]
I/O
DSP#2 & DSP#3 Data bus[4]
62
DG
-
GND
63
DSP_D[3]
I/O
DSP#2 & DSP#3 Data bus[3]
64
DSP_D[2]
I/O
DSP#2 & DSP#3 Data bus[2]
65
DSP_D[1]
I/O
DSP#2 & DSP#3 Data bus[1]
94
KX-NSX1000/KX-NSX2000
Note:
 I/O direction based on Mother board 
66
DSP_D[0]
I/O
DSP#2 & DSP#3 Data bus[0]
67
DG
-
GND
68
DSP#2_DSP_nRST
O
DSP#2 DSP Reset signal
69
DG
-
GND
70
DSP#2_TDM0_DX_DSP
O
DSP#2 TDM Transmission data
71
DSP#2_TDM0_RX_DSP
I
DSP#2 TDM Receive data
72
DSP#2_TDM0_FS_DSP
O
DSP#2 TDM frame
73
DSP#2_TDM0_CK_DSP
O
DSP#2 TDM clock
74
DG
-
GND
75
DSP#2_LAN_RX_XM1
I
DSP#2 Receive data1-
76
DSP#2_LAN_RX_XP1
I
DSP#2 Receive data1+
77
DG
-
GND
78
DSP#2_LAN_TX_XM1
O
DSP#2 Transmission data1-
79
DSP#2_LAN_TX_XP1
O
DSP#2 Transmission data1+
80
DG
-
GND
Pin No.
Signal name
I/O
Function
95
KX-NSX1000/KX-NSX2000
15.1.8.
CN14 (DSP#3 Connector)
Pin No.
Signal name
I/O
Function
1
DG
-
GND
2
DSP_CON_No.
O
Fixed to the High Level by mother board
3
n PRESET(DG)
I
Card detection(not used)
4
DG
-
GND
5
DSP#3_CARD_ID[0]
I
DSP#3 DSP CARD TYPE
6
DSP#3_CARD_ID[1]
I
7
DSP#3_CARD_ID[2]
I
8
DSP#3_CARD_ID[3]
I
9
DSP#3_CARD_ID[4]
I
10
DSP#3_CARD_ID[5]
I
11
DSP#3_CARD_ID[6]
I
12
DG
-
GND
13
DSP#3_CARDID_nOE
O
Output Enable for DSP#3 CARD_ID
14
DG
-
GND
15
DSP_D[8]
I/O
DSP#2 & DSP#3 Data bus[8]
16
DSP_D[9]
I/O
DSP#2 & DSP#3 Data bus[9]
17
DSP_D[10]
I/O
DSP#2 & DSP#3 Data bus[10]
18
DSP_D[11]
I/O
DSP#2 & DSP#3 Data bus[11]
19
DG
-
GND
20
DSP_D[12]
I/O
DSP#2 & DSP#3 Data bus[12]
21
DSP_D[13]
I/O
DSP#2 & DSP#3 Data bus[13]
22
DSP_D[14]
I/O
DSP#2 & DSP#3 Data bus[14]
23
DSP_D[15]
I/O
DSP#2 & DSP#3 Data bus[15]
24
DG
-
GND
25
DSP_A[1]
O
DSP#2 & DSP#3 Address bus[1]
26
DSP_A[2]
O
DSP#2 & DSP#3 Address bus[2]
27
DSP_A[3]
O
DSP#2 & DSP#3 Address bus[3]
28
DSP_A[4]
O
DSP#2 & DSP#3 Address bus[4]
29
DG
-
GND
30
DSP_A[5]
O
DSP#2 & DSP#3 Address bus[5]
31
DSP#3_nRST_PORT_PHY
O
DSP#3 PHY Reset
32
DSP#3_nCS_DSP1
O
DSP#3 Card, chip select for DSP1
33
DG
-
GND
34
DSP_A[6]
DSP#2 & DSP#3 Address bus[6]
35
DSP_A[7]
DSP#2 & DSP#3 Address bus[7]
36
DSP#3_nINT_DSP1
I
DSP#3 Card, DSP1  Interrupt Input
37
DSP#3_nINT_DSP0
I
DSP#3 Card, DSP0  Interrupt Input
38
DG
-
GND
39
NC
40
+15V
-
DC Input +15V
41
+15V
-
DC Input +15V
42
NC
43
DG
-
GND
44
DSP#3_TDM1_DX_DSP
O
DSP#3 TDM Transmission data
45
DSP#3_TDM1_RX_DSP
I
DSP#3 TDM Receive data
46
3R3VA_DSP#3
O
DSP#3 3.3VDC Input for Trans
47
(TDM01_CK)
O
Reserve
48
DG
-
GND
49
DSP#3_nCS_DSP0
O
DSP#3 Card, chip select for DSP0
50
DG
-
GND
51
B_CLK_66M
O
DSP#3 Bus clock
52
DG
-
GND
53
DSP_nRD
O
DSP#2 & DSP#3 Read signal
54
DSP_nWE
O
DSP#2 & DSP#3 Write signal
55
DSP_nBE1
O
DSP#2 & DSP#3 Byte Enable[1]
56
DSP_nBE0
O
DSP#2 & DSP#3 Byte Enable[0]
57
DG
-
GND
58
DSP_D[7]
I/O
DSP#2 & DSP#3 Data bus[7]
59
DSP_D[6]
I/O
DSP#2 & DSP#3 Data bus[6]
60
DSP_D[5]
I/O
DSP#2 & DSP#3 Data bus[5]
61
DSP_D[4]
I/O
DSP#2 & DSP#3 Data bus[4]
62
DG
-
GND
63
DSP_D[3]
I/O
DSP#2 & DSP#3 Data bus[3]
64
DSP_D[2]
I/O
DSP#2 & DSP#3 Data bus[2]
96
KX-NSX1000/KX-NSX2000
Note:
 I/O direction based on Mother board 
15.1.9.
Power Supply Unit I/F & FAN Connector
CN11
CN12
CN13
Note:
 I/O direction based on Mother board 
65
DSP_D[1]
I/O
DSP#2 & DSP#3 Data bus[1]
66
DSP_D[0]
I/O
DSP#2 & DSP#3 Data bus[0]
67
DG
-
GND
68
DSP#3_DSP_nRST
O
DSP#3 DSP Reset signal
69
DG
-
GND
70
DSP#3_TDM0_DX_DSP
O
DSP#3 TDM Transmission data
71
DSP#3_TDM0_RX_DSP
I
DSP#3 TDM Receive data
72
DSP#3_TDM0_FS_DSP
O
DSP#3 TDM frame
73
DSP#3_TDM0_CK_DSP
O
DSP#3 TDM clock
74
DG
-
GND
75
DSP#3_LAN_RX_XM1
I
DSP#3 Receive data1-
76
DSP#3_LAN_RX_XP1
I
DSP#3 Receive data1+
77
DG
-
GND
78
DSP#3_LAN_TX_XM1
O
DSP#3 Transmission data1-
79
DSP#3_LAN_TX_XP1
O
DSP#3 Transmission data1+
80
DG
-
GND
Pin No.
Signal name
I/O
Function
1
+15V
-
DC Input Voltage +15V±1V
2
+15V
-
3
+15V
-
4
NC
-
5
GND
-
Ground
6
GND
-
7
GND
-
8
AC_ALMn_FPGA
I
AC Alarm Signal, Normal:  Low Level  
9
DC_ALMn_FPGA
I
DC Alarm Signal, Normal: Low level
10
NC(BAT2 for checker)
-
Pin No.
Signal Name
I/O
Function
1
DG
-
Ground
2
+12V
-
+12V DC Power supply
3
FAN_ALM#1_FPGA
I
FAN Alarm detection
Pin No.
Signal Name
I/O
Function
1
DG
-
Ground
2
+12V
-
+12V DC Power supply
3
FAN_ALM#2_FPGA
I
FAN Alarm detection
Pin No.
Signal name
I/O
Function
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