Harman Kardon AVR 460 Service Manual ▷ View online
CS42528
18
DS586PP5
AD0/CS
10
Address Bit 0 (I
2
C)/Control Port Chip Select (SPI) (Input
) - AD0 is a chip address pin in I
2
C mode; CS
is the chip select signal in SPI mode.
INT
11
Interrupt
(Output) - The CS42528 will generate an interrupt condition as per the Interrupt Mask register.
See “Interrupts” on page 40 for more details.
RST
12
Reset
(Input) - The device enters a low power mode and all internal registers are reset to their default
settings when low.
AINR-
AINR+
AINR+
13
14
14
Differential Right Channel Analog Input
(Input) - Signals are presented differentially to the delta-sigma
modulators via the AINR+/- pins.
AINL+
AINL-
AINL-
15
16
16
Differential Left Channel Analog Input
(Input) - Signals are presented differentially to the delta-sigma
modulators via the AINL+/- pins.
VQ
17
Quiescent Voltage
(Output) - Filter connection for internal quiescent reference voltage.
FILT+
18
Positive Voltage Reference
(Output) - Positive reference voltage for the internal sampling circuits.
REFGND
19
Reference Ground
(Input) - Ground reference for the internal sampling circuits.
AOUTA1 +,-
AOUTB1 +,-
AOUTA2 +,-
AOUTB2 +,-
AOUTA3 +,-
AOUTB3 +,-
AOUTA4 +,-
AOUTB4 +,-
AOUTB1 +,-
AOUTA2 +,-
AOUTB2 +,-
AOUTA3 +,-
AOUTB3 +,-
AOUTA4 +,-
AOUTB4 +,-
36,37
35,34
32,33
31,30
28,29
27,26
22,23
21,20
35,34
32,33
31,30
28,29
27,26
22,23
21,20
Differential Analog Output
(Output) - The full-scale differential analog output level is specified in the
Analog Characteristics specification table.
VA
VARX
VARX
24
41
41
Analog Power
(Input) - Positive power supply for the analog section.
AGND
25
40
40
Analog Ground
(Input) - Ground reference. Should be connected to analog ground.
MUTEC
38
Mute Control
(Output) - The Mute Control pin outputs high impedance following an initial power-on con-
dition or whenever the PDN bit is set to a ‘1’, forcing the codec into power-down mode. The signal will
remain in a high impedance state as long as the part is in power-down mode. The Mute Control pin goes
to the selected “active” state during reset, muting, or if the master clock to left/right clock frequency ratio
is incorrect. This pin is intended to be used as a control for external mute circuits to prevent the clicks
and pops that can occur in any single supply system. The use of external mute circuits are not manda-
tory but may be desired for designs requiring the absolute minimum in extraneous clicks and pops.
remain in a high impedance state as long as the part is in power-down mode. The Mute Control pin goes
to the selected “active” state during reset, muting, or if the master clock to left/right clock frequency ratio
is incorrect. This pin is intended to be used as a control for external mute circuits to prevent the clicks
and pops that can occur in any single supply system. The use of external mute circuits are not manda-
tory but may be desired for designs requiring the absolute minimum in extraneous clicks and pops.
LPFLT
39
PLL Loop Filter
(Output) - An RC network should be connected between this pin and ground.
RXP7/GPO7
RXP6/GPO6
RXP5/GPO5
RXP4/GPO4
RXP3/GPO3
RXP2/GPO2
RXP1/GPO1
RXP6/GPO6
RXP5/GPO5
RXP4/GPO4
RXP3/GPO3
RXP2/GPO2
RXP1/GPO1
42
43
44
45
46
47
48
43
44
45
46
47
48
S/PDIF Receiver Input/ General Purpose Output
(Input/Output) - Receiver inputs for S/PDIF encoded
data. The CS42528 has an internal 8:2 multiplexer to select the active receiver port, according to the
Receiver Mode Control 2 register. These pins can also be configured as general purpose output pins,
ADC Overflow indicators or Mute Control outputs according to the RXP/General Purpose Pin Control
registers.
Receiver Mode Control 2 register. These pins can also be configured as general purpose output pins,
ADC Overflow indicators or Mute Control outputs according to the RXP/General Purpose Pin Control
registers.
RXP0
49
S/PDIF Receiver Input
(Input) - Dedicated receiver input for S/PDIF encoded data.
TXP
50
S/PDIF Transmitter Output
(Output) - S/PDIF encoded data output, mapped directly from one of the
receiver inputs as indicated by the Receiver Mode Control 2 register.
VLS
53
Serial Port Interface Power
(Input) - Determines the required signal level for the serial port interfaces.
SAI_SDOUT
54
Serial Audio Interface Serial Data Output
(Output) - Output for two’s complement serial audio PCM
data from the S/PDIF incoming stream. This pin can also be configured to transmit the output of the inter-
nal and external ADCs.
nal and external ADCs.
RMCK
55
Recovered Master Clock
(Output) - Recovered master clock output from the External Clock Reference
(OMCK, pin 59) or the PLL which is locked to the incoming S/PDIF stream or CX_LRCK.
harman/kardon
AVR 460/230 Service Manual
Page 53 of 142
DS586PP5
19
CS42528
CX_SDOUT
56
CODEC Serial Data Output
(Output) - Output for two’s complement serial audio data from the internal
and external ADCs.
ADCIN1
ADCIN2
ADCIN2
58
57
57
External ADC Serial Input
(Input) - The CS42528 provides for up to two external stereo analog to digital
converter inputs to provide a maximum of six channels on one serial data output line when the CS42528
is placed in One Line mode.
is placed in One Line mode.
OMCK
59
External Reference Clock
(Input) - External clock reference that must be within the ranges specified in
the register “OMCK Frequency (OMCK Freqx)” on page 54.
SAI_LRCK
60
Serial Audio Interface Left/Right Clock
(Input/Output) - Determines which channel, Left or Right, is
currently active on the serial audio data line.
SAI_SCLK
61
Serial Audio Interface Serial Clock
(Input/Output) - Serial clock for the Serial Audio Interface.
harman/kardon
AVR 460/230 Service Manual
Page 54 of 142
DS752PP7
Copyright 2008 Cirrus Logic
31
CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
8. Device Pin-Out Diagram
8.1 128-Pin LQFP Pin-Out Diagram
Figure 20.
128-Pin LQFP Pin-Out Diagram
GPIO2, UART_TXD
GPIO1, UART_RXD
GPIO0, UART_CLK, EE_CS#
XTO
VDD7
GND7
VDDIO7
XTI
GNDIO7
GNDA
PLL_REF_RES
VDDA (3.3V)
VDD8
GND8
GPIO13, DAI1_DATA2, TM2, DSD2
GPIO14, DAI1_DATA3, TM3, DSD3
DAI1_DATA0, TM0, DSD0
GPIO12, DAI1_DATA1, TM1, DSD1
GPIO6, PCP_CS#, SCP2_CS#
GPIO38, PCP_WR# / DS#, SCP2_CLK
VD
D
6
GN
D
6
GPIO10, PCP_A2 / A10, SCP2_MOSI
GPIO8, PCP_IRQ#, SCP2_IRQ#
GPI
O37,
SC
P1_B
SY#,
PC
P_B
S
Y
#
VD
D
IO6
GPIO11, PCP_A3, AS#, SCP2_MISO / SDA
GN
D
IO6
GPOI9, SCP1_IRQ#
GPI
O34,
SC
P1__M
ISO /
SD
A
GPI
O33,
SC
P1_M
OSI
GPI
O35,
SC
P1_C
L
K
VD
D
5
VDDIO5
GN
D
5
GN
D
IO5
SD
_C
A
S#
SD
_R
A
S#
SD_A3, EXT_A3
SD_A2, EXT_A2
SD_A1, EXT_A1
SD_A0, EXT_A0
SD
_A
10,
EXT
_A
10
SD_A11, EXT_A11
VDD4
GND4
SD
_C
S#
SD_A4, EXT_A4
SD_A5, EXT_A5
SD_A6, EXT_A6
SD_A7, EXT_A7
SD_A8, EXT_A8
SD_CLKEN
SD_A9, EXT_A9
VDDIO4
GNDIO4
SD_CLKOUT
SD_CLKIN
SD_D10, EXT_D10
SD_D11, EXT_D11
SD_D12, EXT_D12
VDD3
GND3
SD_D13, EXT_D13
SD_D14, EXT_D14
SD_D15, EXT_D15
SD_DQM1
SD
_D
7,
EXT
_D
7
SD
_D
6,
EXT
_D
6
VDDIO3
GNDIO3
SD
_D
5,
EXT
_D
5
SD
_
D
Q
M
0
SD
_D
4,
EXT
_D
4
SD
_D
3,
EXT
_D
3
SD
_D
2,
EXT
_D
2
G
P
IO
1
7
,
D
AO
1
_
D
AT
A3
/ X
M
TA
GPI
O15,
D
A
O1_D
A
T
A
1,
H
S1
D
AO
1
_
D
AT
A0
, HS
0
DA
O
1
_
L
R
CL
K
DAI1_LRCLK, DSD4
DA
O
_
M
CL
K
GPIO20, DAO2_DATA2
DAI1_SCLK, DSD-CLK
VD
D
1
GN
D
1
DA
O
1
_
S
CL
K
GPI
O16,
D
A
O1_D
A
T
A
2,
H
S2
G
P
IO
2
3
,
DA
O
2
_
L
R
CL
K
R
ESET
#
VD
D
IO1
GPI
O22,
D
A
O2_
S
C
L
K
GN
D
IO1
G
P
IO
1
8
, DA
O
2
_
D
AT
A0
,
H
S
3
G
P
IO
1
9
, DA
O
2
_
D
AT
A1
,
H
S
4
VD
D
2
GN
D
2
GPIO26, DAO2_DATA3 / XMTB/UART_TX_EN
VD
D
IO2
GNDIO2
SD
_W
E#
SD_D0, EXT_D0
SD_D1, EXT_D1
SD_D8, EXT_D8
SD_D9, EXT_D9
SD_A12, EXT_A12
SD
_B
A
1,
EXT
_A
14
SD
_B
A
0,
EXT
_A
13
GPIO7, SCP1_CS#, IOWAIT
VDDIO8
GNDIO8
EXT
_A
15
EXT
_A
16
EXT
_A
17
EXT
_A
18
EXT
_A
19
EXT
_C
S1#
EXT
_OE#
EXT_WE#
GPIO3, DDAC
TE
S
T
DBDA
DBCK
XTAL_OUT
GPIO43, BDI_CLK, DAI2_SCLK
GPIO42, BDI_REQ# , DAI2_LRCLK, PCP_IRQ# / BSY#
BDI_DATA, DAI2_DATA, DSD5
EXT_CS2#
10
15
20
25
30
5
35
1
125
120
115
110
105
95
90
85
80
75
70
65
100
40
45
50
55
60
CS497xx4
128-Pin LQFP
harman/kardon
AVR 460/230 Service Manual
Page 55 of 142
32
Copyright 2008 Cirrus Logic
DS752PP7
CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
32-bit High Definition Audio Decoder DSP Family
8.2 144-Pin LQFP Pin-Out Diagram
Figure 21. 144-Pin LQFP Pin-Out Diagram
G
P
IO
1
1
, PC
P_
A
3
, A
S
#
,
SC
P2
_
M
ISO
/ SD
A
SD_A11, EXT_A11
GPIO26
G
PIO
2
1
, D
A
O
2
_
D
A
T
A
3
/ XM
T
B
, U
A
R
T
_
T
X_
EN
A
B
L
E
SD_A12, EXT_A12
GPIO42, BDI_REQ# , DAI2_LRCLK, PCP_IRQ# / BSY#
113
116
119
122
126
129
130
133
136
139
109
110
115
120
125
135
140
144
CS497xx4
144-Pin LQFP
G
P
IO
2
5
, UART
_
T
X
D
,
E
E
_
C
S
#
G
P
IO
24,
U
A
R
T
_R
X
D
G
P
IO
3
1
, UA
RT
_
C
L
K
SD
_
D
7
, EXT
_
D
7
SD
_
D
6
, EXT
_
D
6
SD
_
D
5
, EXT
_
D
5
SD
_
D
Q
M
0
SD
_
D
4
, EXT
_
D
4
SD
_
D
3
, EXT
_
D
3
S
D
_D
2,
E
X
T
_
D
2
G
P
IO
17,
D
A
O1
_D
A
T
A
3 /
X
M
T
A
G
P
IO
1
5
, D
A
O
1
_
DAT
A1
, H
S
1
D
AO
1
_
DAT
A0
, H
S
0
D
A
O
1_L
R
C
L
K
DA
O
_
M
C
L
K
G
P
IO
2
0
, D
A
O
2
_
DAT
A2
V
DD1
G
ND1
DA
O
1
_
S
CL
K
G
P
IO
1
6
, D
A
O
1
_
DAT
A2
, H
S
2
G
P
IO
23
, D
A
O
2_L
R
C
L
K
VD
D
IO
1
G
P
IO
2
2
, D
A
O
2
_
S
CL
K
GN
D
IO1
G
P
IO
1
8
, D
A
O
2
_
DAT
A0
, H
S
3
G
P
IO
19,
D
A
O2
_D
A
T
A
1,
H
S
4
V
DD2
G
ND2
VD
D
IO
2
G
NDI
O
2
G
P
IO
2
8
, DDA
C
GP
IO
29,
X
M
T
A
_
IN
T
EST
DB
DA
DB
CK
1
5
9
10
13
18
21
24
27
33
36
15
25
30
35
SD_A3, EXT_A3
SD_A2, EXT_A2
SD_A1, EXT_A1
SD_A0, EXT_A0
VDD4
GND4
SD_A4, EXT_A4
SD_A5, EXT_A5
SD_A6, EXT_A6
SD_A7, EXT_A7
SD_A8, EXT_A8
SD_CLKEN
SD_A9, EXT_A9
VDDIO4
GNDIO4
SD_CLKOUT
SD_CLKIN
SD_D10, EXT_D10
SD_D11, EXT_D11
SD_D12, EXT_D12
VDD3
GND3
SD_D13, EXT_D13
SD_D14, EXT_D14
SD_D15, EXT_D15
SD_DQM1
VDDIO3
GNDIO3
SD_D0, EXT_D0
SD_D1, EXT_D1
SD_D8, EXT_D8
SD_D9, EXT_D9
EXT_CS2#
EXT_WE#
69
66
63
60
57
54
47
44
37
40
45
50
55
65
70
72
G
P
IO
3
9
, PC
P_
C
S
#
, SC
P
2
_
C
S#
G
P
IO
3
8
, PC
P_
W
R
#
/
D
S
#
, SC
P2
_
C
L
K
VD
D
6
G
P
IO
4
0
, PC
P_
R
D
#
/ RW
#
G
ND6
G
P
IO
1
0
, PC
P_
A
2
/
A
1
0
,
SC
P2
_
M
O
S
I
G
P
IO
4
1
, PC
P_
IR
Q
#
, SC
P2
_
IR
Q
#
G
P
IO
3
7
, SC
P1
_
B
SY#
, PC
P_
B
SY#
V
DDIO
6
G
NDIO
6
G
P
OI
36,
S
C
P
1
_
IR
Q#
G
P
IO
3
4
, SCP1
_
_
M
ISO
/ S
D
A
GP
IO
33,
S
C
P
1_M
OS
I
GP
IO
35,
S
C
P
1_C
L
K
VD
D
5
VD
D
IO
5
G
ND5
G
NDIO
5
SD
_
C
A
S
#
SD
_
R
A
S
#
S
D
_A
1
0
, E
X
T
_A
10
SD
_
C
S
#
R
ESET
#
SD
_
W
E
#
S
D
_B
A
1,
E
X
T
_A
1
4
SD
_
B
A
0
, EXT
_
A
1
3
G
P
IO
3
2
, SC
P1
_
C
S#
, IO
W
A
IT
EXT
_
A
1
5
EXT
_
A
1
6
EXT
_
A
1
7
EXT
_
A
1
8
EXT
_
A
1
9
EXT
_
C
S1
#
EXT
_
O
E#
GP
IO
30,
X
M
T
B
_I
N
10
1
98
94
91
86
83
76
73
75
80
85
90
95
10
0
10
5
10
8
GPIO1, PCP_AD1 / D1
GPIO0, PCP_AD0 / D0
XTO
VDD7
GND7
VDDIO7
XTI
GNDIO7
GNDA
NC
PLL_REF_RES
VDDA (3.3V)
VDD8
GND8
GPIO13, DAI1_DATA2, TM2, DSD2
GPIO14, DAI1_DATA3, TM3, DSD3
DAI1_DATA0, TM0, DSD0
GPIO12, DAI1_DATA1, TM1, DSD1
GPIO2, PCP_AD2 / D2
GPIO3, PCP_AD3 / D3
GPIO4, PCP_AD4 / D4
GPIO5, PCP_AD5 / D5
GPIO6, PCP_AD6 / D6
GPIO7, PCP_AD7 / D7
GPIO9, PCP_A1 / A9
DAI1_LRCLK, DSD4
DAI1_SCLK, DSD-CLK
VDDIO8
GNDIO8
GPIO8, PCP_A0 / A8
GPIO27
XTAL_OUT
GPIO43, BDI_CLK, DAI2_SCLK
BDI_DATA, DAI2_DATA, DSD5
harman/kardon
AVR 460/230 Service Manual
Page 56 of 142
Click on the first or last page to see other AVR 460 service manuals if exist.