Harman Kardon AVR 460 Service Manual ▷ View online
ADV7342/ADV7343
Rev. 0 | Page 19 of 88
Pin No.
Mnemonic
Input/
Output
Output
Description
36 R
SET2
I
This pin is used to control the amplitudes of the DAC 4, DAC 5, and DAC 6 outputs. A 4.12 kΩ
resistor must be connected from R
resistor must be connected from R
SET2
to AGND.
45, 35
COMP1,
COMP2
COMP2
O
Compensation Pins. Connect a 2.2 nF capacitor from both COMP pins to V
AA
.
44, 43, 42
DAC 1, DAC 2,
DAC 3
DAC 3
O
DAC Outputs. Full and low drive capable DACs.
39, 38, 37
DAC 4, DAC 5,
DAC 6
DAC 6
O
DAC Outputs. Low drive only capable DACs.
21
SCL/MOSI
I
Multifunctional Pin: I
2
C Clock Input/SPI Data Input.
20
SDA/SCLK
I/O
Multifunctional Pin: I
2
C Data Input/Output. Also, SPI clock input.
19
ALSB/SPI_SS
I
Multifunctional Pin: This signal sets up the LSB
2
of the MPU I
2
C address. Also, SPI slave select.
46 V
REF
Optional External Voltage Reference Input for DACs or Voltage Reference Output.
41 V
AA
P
Analog Power Supply (3.3 V).
10, 56
V
DD
P
Digital Power Supply (1.8 V). For dual-supply configurations, V
DD
can be connected to other 1.8 V
supplies through a ferrite bead or suitable filtering.
1 V
DD_IO
P
Input/Output Digital Power Supply (3.3 V).
34 PV
DD
P
PLL Power Supply (1.8 V). For dual-supply configurations, PV
DD
can be connected to other 1.8 V
supplies through a ferrite bead or suitable filtering.
33
EXT_LF1
I
External Loop Filter for On-Chip PLL 1.
31
EXT_LF2
I
External Loop Filter for On-Chip PLL 2.
32
PGND
G
PLL Ground Pin.
40
AGND
G
Analog Ground Pin.
11, 57
DGND
G
Digital Ground Pin.
64
GND_IO
G
Input/Output Supply Ground Pin.
1
ED = enhanced definition = 525p and 625p.
2
LSB = least significant bit. In the ADV7342, setting the LSB to 0 sets the I
2
C address to 0xD4. Setting it to 1 sets the I
2
C address to 0xD6. In the ADV7343, setting the
LSB to 0 sets the I
2
C address to 0x54. Setting it to 1 sets the I
2
C address to 0x56.
harman/kardon
AVR 460/230 Service Manual
Page 49 of 142
1
Features
•
Low-voltage and Standard-voltage Operation
– 2.7 (V
CC
= 2.7V to 5.5V)
– 1.8 (V
CC
= 1.8V to 5.5V)
•
Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),
1024 x 8 (8K) or 2048 x 8 (16K)
1024 x 8 (8K) or 2048 x 8 (16K)
•
Two-wire Serial Interface
•
Schmitt Trigger, Filtered Inputs for Noise Suppression
•
Bidirectional Data Transfer Protocol
•
100 kHz (1.8V) and 400 kHz (2.7V, 5V) Compatibility
•
Write Protect Pin for Hardware Data Protection
•
8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes
•
Partial Page Writes Allowed
•
Self-timed Write Cycle (5 ms max)
•
High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
– Data Retention: 100 Years
•
Automotive Grade and Lead-free/Halogen-free Devices Available
•
8-lead PDIP, 8-lead JEDEC SOIC, 8-lead MAP, 5-lead SOT23,
8-lead TSSOP and 8-ball dBGA2 Packages
8-lead TSSOP and 8-ball dBGA2 Packages
•
Die Sales: Wafer Form, Waffle Pack and Bumped Wafers
Description
The AT24C01A/02/04/08A/16A provides 1024/2048/4096/8192/16384 bits of serial
electrically erasable and programmable read-only memory (EEPROM) organized as
128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage operation
are essential. The AT24C01A/02/04/08A/16A is available in space-saving 8-lead PDIP,
8-lead JEDEC SOIC, 8-lead MAP, 5-lead SOT23 (AT24C01A/AT24C02/AT24C04), 8-
lead TSSOP, and 8-ball dBGA2 packages and is accessed via a Two-wire serial inter-
face. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to
5.5V) versions.
electrically erasable and programmable read-only memory (EEPROM) organized as
128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage operation
are essential. The AT24C01A/02/04/08A/16A is available in space-saving 8-lead PDIP,
8-lead JEDEC SOIC, 8-lead MAP, 5-lead SOT23 (AT24C01A/AT24C02/AT24C04), 8-
lead TSSOP, and 8-ball dBGA2 packages and is accessed via a Two-wire serial inter-
face. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to
5.5V) versions.
Table 1. Pin Configuration
Pin Name
Function
A0 - A2
Address Inputs
SDA
Serial Data
SCL
Serial Clock Input
WP
Write Protect
NC
No Connect
GND
Ground
VCC
Power Supply
Two-wire
Serial EEPROM
Serial EEPROM
1K (128 x 8)
2K (256 x 8)
4K (512 x 8)
8K (1024 x 8)
16K (2048 x 8)
AT24C01A
AT24C02
AT24C04
AT24C08A
AT24C16A
AT24C02
AT24C04
AT24C08A
AT24C16A
0180V–SEEPR–8/05
8-lead SOIC
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
8-lead PDIP
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
8-lead MAP
Bottom View
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
A2
GND
5-lead SOT23
1
2
3
5
4
SCL
GND
SDA
WP
VCC
8-ball dBGA2
Bottom View
VCC
WP
SCL
SDA
A0
A1
A2
GND
1
2
3
4
8
7
6
5
8-lead TSSOP
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
harman/kardon
AVR 460/230 Service Manual
Page 50 of 142
28
Copyright 2008 Cirrus Logic, Inc.
DS868PP2
CS49DV8C Data Sheet
32-bit Audio DSP Family
32-bit Audio DSP Family
8. Device Pin-Out Diagram
8.1 128-Pin LQFP Pin-Out Diagram
Figure 15. 128-Pin LQFP Pin-Out
GPIO2, UART_TXD
GPIO1, UART_RXD
GPIO0, UART_CLK
XTO
VDD7
GND7
VDDIO7
XTI
GNDIO7
GNDA
PLL_REF_RES
VDDA (3.3V)
VDD8
GND8
GPIO13, DAI1_DATA2, TM2, DSD2
GPIO14, DAI1_DATA3, TM3, DSD3
DAI1_DATA0, TM0, DSD0
GPIO12, DAI1_DATA1, TM1, DSD1
GPIO6, PCP_CS#, SCP2_CS#
GPIO38, PCP_WR# / DS#, SCP2_CLK
VD
D
6
GN
D
6
GPIO10, PCP_A2 / A10, SCP2_MOSI
GPIO8, PCP_IRQ#, SCP2_IRQ#
G
P
IO
37
, S
C
P
1
_
B
SY#
,
PC
P_B
S
Y
#
VD
D
IO
6
GPIO11, PCP_A3, AS#, SCP2_MISO / SDA
GN
D
IO
6
GPOI9, SCP1_IRQ#
G
P
IO
3
4
, S
C
P
1
_
_
M
ISO /
SD
A
G
P
IO
3
3
, S
C
P
1
_
M
OSI
G
P
IO
3
5
, S
C
P
1
_
C
L
K
VD
D
5
VDDIO5
GN
D
5
GN
D
IO
5
S
D_
CAS
#
S
D_
RAS
#
SD_A3, EXT_A3
SD_A2, EXT_A2
SD_A1, EXT_A1
SD_A0, EXT_A0
SD
_
A
10
, E
X
T
_A
10
SD_A11, EXT_A11
VDD4
GND4
SD
_
C
S#
SD_A4, EXT_A4
SD_A5, EXT_A5
SD_A6, EXT_A6
SD_A7, EXT_A7
SD_A8, EXT_A8
SD_CLKEN
SD_A9, EXT_A9
VDDIO4
GNDIO4
SD_CLKOUT
SD_CLKIN
SD_D10, EXT_D10
SD_D11, EXT_D11
SD_D12, EXT_D12
VDD3
GND3
SD_D13, EXT_D13
SD_D14, EXT_D14
SD_D15, EXT_D15
SD_DQM1
SD
_D
7,
EX
T
_
D
7
SD
_D
6,
EX
T
_
D
6
VDDIO3
GNDIO3
SD
_D
5,
EX
T
_
D
5
SD
_
D
Q
M
0
SD
_D
4,
EX
T
_
D
4
SD
_D
3,
EX
T
_
D
3
SD
_D
2,
EX
T
_
D
2
G
P
IO
1
7
, DAO
1
_
DATA
3
/
X
M
TA
G
P
IO
1
5
, D
AO
1
_
D
ATA1
,
HS
1
D
AO
1
_
D
ATA0
, HS
0
DAO
1
_
LRCLK
DAI1_LRCLK, DSD4
DA
O
_
M
C
L
K
GPIO20, DAO2_DATA2, EE_CS#
DAI1_SCLK, DSD-CLK
V
DD1
G
ND1
DA
O
1
_
S
CLK
G
P
IO
1
6
, D
AO
1
_
D
ATA2
,
HS
2
GP
IO2
3
,
DAO
2
_
LRCLK
RE
S
E
T#
V
DDI
O
1
G
P
IO
2
2
, DA
O
2
_
S
CLK
G
NDI
O
1
G
P
IO
1
8
, D
AO
2
_
DATA0
, HS
3
G
P
IO
1
9
, D
AO
2
_
DATA1
, HS
4
V
DD2
G
ND2
GPIO26, DAO2_DATA3 / XMTB/UART_TX_EN
V
DDI
O
2
GNDIO2
SD
_
W
E
#
SD_D0, EXT_D0
SD_D1, EXT_D1
SD_D8, EXT_D8
SD_D9, EXT_D9
SD_A12, EXT_A12
S
D
_
BA1
, E
X
T_
A1
4
S
D
_
BA0
, E
X
T_
A1
3
GPIO7, SCP1_CS#, IOWAIT
VDDIO8
GNDIO8
EX
T
_
A
1
5
EX
T
_
A
1
6
EX
T
_
A
1
7
EX
T
_
A
1
8
EX
T
_
A
1
9
EX
T
_
C
S
1
#
EX
T
_
O
E
#
EXT_WE#
GPIO3, DDAC
TE
S
T
DBDA
DBCK
XTAL_OUT
GPIO43, BDI_CLK, DAI2_SCLK
GPIO42, BDI_REQ# , DAI2_LRCLK, PCP_IRQ# / BSY#
BDI_DATA, DAI2_DATA, DSD5
EXT_CS2#
10
15
20
25
30
5
35
1
125
120
115
110
105
95
90
85
80
75
70
65
100
40
45
50
55
60
128-Pin LQFP
harman/kardon
AVR 460/230 Service Manual
Page 51 of 142
DS586PP5
17
CS42528
2. PIN DESCRIPTIONS
Pin Name
#
Pin Description
CX_SDIN1
CX_SDIN2
CX_SDIN3
CX_SDIN4
CX_SDIN2
CX_SDIN3
CX_SDIN4
1
64
63
62
63
62
Codec Serial Audio Data Input
(Input) - Input for two’s complement serial audio data.
CX_SCLK
2
CODEC Serial Clock
(Input/Output) - Serial clock for the CODEC serial audio interface.
CX_LRCK
3
CODEC Left Right Clock
(Input/Output) - Determines which channel, Left or Right, is currently active on
the CODEC serial audio data line.
VD
4
51
Digital Power
(Input) - Positive power supply for the digital section.
DGND
5
52
Digital Ground
(Input) - Ground reference. Should be connected to digital ground.
VLC
6
Control Port Power
(Input) - Determines the required signal level for the control port.
SCL/CCLK
7
Serial Control Port Clock
(Input) - Serial clock for the serial control port. Requires an external pull-up
resistor to the logic interface voltage in I
2
C mode as shown in the Typical Connection Diagram.
SDA/CDOUT
8
Serial Control Data
(Input/Output) - SDA is a data I/O line in I
2
C mode and requires an external pull-up
resistor to the logic interface voltage, as shown in the Typical Connection Diagram. CDOUT is the output
data line for the control port interface in SPI mode.
data line for the control port interface in SPI mode.
AD1/CDIN
9
Address Bit 1 (I
2
C)/Serial Control Data (SPI)
(Input) - AD1 is a chip address pin in I
2
C mode; CDIN is
the input data line for the control port interface in SPI mode.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
CX_SDIN1
SAI
_
SC
L
K
SAI
_
L
R
C
K
VD
DGND
VLC
SCL/CCLK
SDA/CDOUT
AD1/CDIN
AD0/CS
INT
RST
AINR-
AINR+
AINL+
AINL-
VQ
FI
L
T
+
RE
F
G
ND
AO
U
T
B
4
-
AO
U
T
B
4
+
AO
U
T
A
4
+
AO
UT
A
4
-
VA
AG
N
D
AO
U
T
B
3
-
AO
U
T
B3
+
AO
U
T
A3
+
AO
U
T
A
3
-
AO
UT
B
2
-
AO
U
T
B2
+
AO
U
T
A2
+
AOUTA2-
AOUTB1-
AOUTB1+
AOUTA1+
AOUTA1-
MUTEC
AGND
VARX
RXP7/GPO7
RXP6/GPO6
RXP5/GPO5
RXP4/GPO4
RXP3/GPO3
RXP2/GPO2
RXP1/GPO1
LPFLT
RX
P
0
TXP
VD
DG
ND
VL
S
SAI
_
SD
O
U
T
RM
CK
CX
_
S
DO
UT
A
D
CI
N2
A
D
CI
N1
OMC
K
CX_LRCK
CX_SCLK
CX
_
S
DI
N4
CX
_
S
DI
N3
C
X
_
S
DI
N2
CS42528
harman/kardon
AVR 460/230 Service Manual
Page 52 of 142
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