Harman Kardon AVR 460 Service Manual ▷ View online
1
IDT74FCT38072
3.3V CMOS 1-TO-2 CLOCK DRIVER
3.3V CMOS 1-TO-2 CLOCK DRIVER
INDUSTRIAL TEMPERATURE RANGE
AUGUST 2004
2004 Integrated Device Technology, Inc.
DSC-6595/5
c
IDT74FCT38072
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS
1-TO-2 CLOCK DRIVER
1-TO-2 CLOCK DRIVER
DESCRIPTION:
The FCT38072 is a 3.3V clock driver built using advanced CMOS
technology. This low skew clock driver offers 1:2 fanout. The large fanout from
a single input reduces loading on the preceding driver and provides an efficient
clock distribution network. Multiple power and grounds reduce noise. Typical
applications are clock and signal distribution.
a single input reduces loading on the preceding driver and provides an efficient
clock distribution network. Multiple power and grounds reduce noise. Typical
applications are clock and signal distribution.
FUNCTIONAL BLOCK DIAGRAM
IN
O
1
O
2
PIN CONFIGURATION
V
CC
GND
GND
GND
V
CC
IN
O
2
O
1
1
2
3
4
5
6
7
8
SOIC
TOP VIEW
FEATURES:
• Advanced CMOS Technology
• Guaranteed low skew < 100ps (max.)
• Very low duty cycle distortion< 350ps (max.)
• High speed propagation delay< 3ns (max.)
• Very low CMOS power levels
• TTL compatible inputs and outputs
• 1:2 fanout
• Maximum output rise and fall time < 1ns (max.)
• Low input capacitance: 3pF typical
• V
• Guaranteed low skew < 100ps (max.)
• Very low duty cycle distortion< 350ps (max.)
• High speed propagation delay< 3ns (max.)
• Very low CMOS power levels
• TTL compatible inputs and outputs
• 1:2 fanout
• Maximum output rise and fall time < 1ns (max.)
• Low input capacitance: 3pF typical
• V
CC
= 3.3V ± 0.3V
• Inputs can be driven from 3.3V or 5V components
• Operating frequency up to 166MHz
• Available in SOIC package
• Operating frequency up to 166MHz
• Available in SOIC package
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
harman/kardon
AVR 460/230 Service Manual
Page 45 of 142
harman/kardon
AVR 460/230 Service Manual
Page 46 of 142
3
Revision 1.9
256M Double Data Rate Synchronous DRAM
A3S56D30ETP
A3S56D40ETP
A3S56D40ETP
Pin Assignment (Top View) 66-pin TSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VDD
DQ0
DQ0
VDDQ
DQ1
DQ2
DQ2
VSSQ
DQ3
DQ4
DQ4
VDDQ
DQ5
DQ6
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
/WE
/CAS
/RAS
/RAS
/CS
NC
BA0
BA1
BA1
A10/AP
A0
A1
A2
A3
A1
A2
A3
VDD
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
/CLK
CLK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
66pin TSOP(II)
400mil width
x
875mil length
0.65mm
Lead Pitch
Row
A0-12
Column
A0-9 (x8)
A0-8 (x16)
VDD
DQ0
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
NC
VDDQ
NC
NC
NC
VDD
NC
NC
NC
/WE
/CAS
/RAS
/RAS
/CS
NC
BA0
BA1
BA1
A10/AP
A0
A1
A2
A3
A1
A2
A3
VDD
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CLK
CLK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
x8
x16
CLK, /CLK
CKE
/CS
/RAS
/CAS
/WE
DQ0-15
UDM, LDM
DM
DQ0-7
UDQS, LDQS
DQS
: Master Clock
: Clock Enable
: Chip Select
: Row Address Strobe
: Column Address Strobe
: Write Enable
: Data I/O (x16)
: Write Mask (x16)
: Write Mask (x8)
: Data I/O (x8)
: Data Strobe (x16)
: Data Strobe (x8)
A0-12
BA0,1
Vdd
VddQ
Vss
VssQ
: Address Input
: Bank Address Input
: Power Supply
: Power Supply for Output
: Ground
: Ground for Output
harman/kardon
AVR 460/230 Service Manual
Page 47 of 142
ADV7342/ADV7343
Rev. 0 | Page 18 of 88
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
64
G
ND_I
O
63
CL
KI
N_B
62
S7
61
S6
60
S5
59
S4
58
S3
57
DG
ND
56
V
DD
55
S2
54
S1
53
S0
52
TE
S
T
5
51
TE
S
T
4
50
S_
H
S
YN
C
49
S_
VS
YN
C
47
R
SET1
46
V
REF
45
COMP1
42
DAC 3
43
DAC 2
44
DAC 1
48
SFL/MISO
41
V
AA
40
AGND
39
DAC 4
37
DAC 6
36
R
SET2
35
COMP2
34
PV
DD
33
EXT_LF1
38
DAC 5
2
TEST0
3
TEST1
4
Y0
7
Y3
6
Y2
5
Y1
1
V
DD_IO
8
Y4
9
Y5
10
V
DD
12
Y6
13
Y7
14
TEST2
15
TEST3
16
C0
11
DGND
17
C1
18
C2
19
A
L
SB
/S
PI
_SS
20
S
DA/
S
CL
K
21
SC
L
/M
O
SI
22 23
P_
H
SY
N
C
24
P_
V
SYN
C
25
P
_BL
AN
K
26
C4
C3
27
C5
28
C6
29
C7
30
CL
KI
N_A
31 32
PG
N
D
PIN 1
ADV7342/ADV7343
TOP VIEW
(Not to Scale)
EX
T
_L
F
2
06
39
9-
02
1
Figure 21. Pin Configuration
Table 13. Pin Function Descriptions
Pin No.
Mnemonic
Input/
Output
Output
Description
13, 12,
9 to 4
9 to 4
Y7 to Y0
I
8-Bit Pixel Port. Y0 is the LSB. Refer to Table 31 for input modes.
29 to 25,
18 to 16
18 to 16
C7 to C0
I
8-Bit Pixel Port. C0 is the LSB. Refer to Table 31 for input modes.
62 to 58,
55 to 53
55 to 53
S7 to S0
I
8-Bit Pixel Port. S0 is the LSB. Refer to Table 31 for input modes.
52, 51, 15,
14, 3, 2
14, 3, 2
TEST5 to
TEST0
TEST0
I
Unused. These pins should be connected to DGND.
30
CLKIN_A
I
Pixel Clock Input for HD Only (74.25 MHz), ED
1
Only (27 MHz or 54 MHz) or SD Only (27 MHz).
63 CLKIN_B
I Pixel Clock Input for Dual Modes Only. Requires a 27 MHz reference clock for ED operation or a
74.25 MHz reference clock for HD operation.
50
S_HSYNC
I/O
SD Horizontal Synchronization Signal. This pin can also be configured to output an SD, ED, or HD
horizontal synchronization signal. See the External Horizontal and Vertical Synchronization
Control section.
horizontal synchronization signal. See the External Horizontal and Vertical Synchronization
Control section.
49
S_VSYNC
I/O
SD Vertical Synchronization Signal. This pin can also be configured to output an SD, ED, or HD
vertical synchronization signal. See the External Horizontal and Vertical Synchronization Control
section.
vertical synchronization signal. See the External Horizontal and Vertical Synchronization Control
section.
22
P_HSYNC
I
ED/HD Horizontal Synchronization Signal. See the External Horizontal and Vertical
Synchronization Control section.
Synchronization Control section.
23
P_VSYNC
I
ED/HD Vertical Synchronization Signal. See the External Horizontal and Vertical Synchronization
Control section.
Control section.
24
P_BLANK
I
ED/HD Blanking Signal. See the External Horizontal and Vertical Synchronization Control section.
48 SFL/MISO
I/O Multifunctional Pin: Subcarrier Frequency Lock (SFL) Input/SPI Data Output. The SFL input is
used to drive the color subcarrier DDS system, timing reset, or subcarrier reset.
47 R
SET1
I
This pin is used to control the amplitudes of the DAC 1, DAC 2, and DAC 3 outputs. For full-drive
operation (for example, into a 37.5 Ω load), a 510 Ω resistor must be connected from R
operation (for example, into a 37.5 Ω load), a 510 Ω resistor must be connected from R
SET1
to
AGND. For low drive operation (for example, into a 300 Ω load), a 4.12 kΩ resistor must be
connected from R
connected from R
SET1
to AGND.
harman/kardon
AVR 460/230 Service Manual
Page 48 of 142
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