Harman Kardon AVR 460 Service Manual ▷ View online
harman/kardon
AVR 460/230 Service Manual
Page 69 of 142
harman/kardon
AVR 460/230 Service Manual
Page 70 of 142
ESMT
M12L16161A
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2005
Revision : 2.4
2/30
SDRAM
512K x 16Bit x 2Banks
Synchronous
DRAM
FEATURES
z
JEDEC standard 3.3V power supply
z
LVTTL compatible with multiplexed address
z
Dual banks operation
z
MRS cycle with address key programs
-
-
CAS Latency (2 & 3 )
-
Burst Length (1, 2, 4, 8 & full page)
-
Burst Type (Sequential & Interleave)
z
All inputs are sampled at the positive going edge of the
system clock
z
Burst Read Single-bit Write operation
z
DQM for masking
z
Auto & self refresh
z
32ms refresh period (2K cycle)
GENERAL DESCRIPTION
The M12L16161A is 16,777,216 bits synchronous high
data rate Dynamic RAM organized as 2 x 524,288 words by
16 bits, fabricated with high performance CMOS technology.
Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.
16 bits, fabricated with high performance CMOS technology.
Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.
ORDERING INFORMATION
Part NO.
MAX Freq.
PACKAGE COMMENTS
M12L16161A-5TG
200MHz
TSOP(II) Pb-free
M12L16161A-7TG
143MHz
TSOP(II) Pb-free
M12L16161A-7BG
143MHz
VFBGA Pb-free
PIN CONFIGURATION (TOP VIEW)
V
DD
DQ0
DQ1
V
DQ1
V
SSQ
DQ2
DQ3
V
DQ3
V
DDQ
DQ4
DQ5
V
DQ5
V
SSQ
DQ6
DQ7
V
DQ7
V
DDQ
LDQM
WE
CAS
RAS
CS
BA
A10/AP
A0
A1
A2
A3
V
WE
CAS
RAS
CS
BA
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
V
SS
DQ15
DQ14
V
DQ14
V
SSQ
DQ13
DQ12
V
DQ12
V
DDQ
DQ11
DQ10
V
DQ10
V
SSQ
DQ9
DQ8
V
DQ8
V
DDQ
N.C/RFU
UDQM
CLK
CKE
N.C
A9
A8
A7
A6
A5
A4
V
UDQM
CLK
CKE
N.C
A9
A8
A7
A6
A5
A4
V
SS
50PIN TSOP(II)
(400mil x 825mil)
(0.8 mm PIN PITCH)
(400mil x 825mil)
(0.8 mm PIN PITCH)
VSS
DQ15
DQ14
VSSQ
DQ13
VDDQ
DQ12
DQ11
DQ10
VSSQ
DQ9
VDDQ
DQ8
NC
NC
NC
NC
UDQM
NC
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
VSS
A4
DQ0
VDD
VDDQ
DQ1
VSSQ
DQ2
DQ4
DQ3
VDDQ
DQ5
VSSQ
DQ6
NC
DQ7
NC
NC
LDQM
WE
CAS
NC
CS
NC
NC
A0
A10
A2
A1
A3
VDD
1
2
3
4
5
6
7
RAS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
60 Ball VFBGA
(6.4x10.1mm)
(0.65mm ball pitch)
harman/kardon
AVR 460/230 Service Manual
Page 71 of 142
M24C64, M24C32
4/26
SUMMARY DESCRIPTION
These I
2
C-compatible electrically erasable pro-
grammable memory (EEPROM) devices are orga-
nized as 8192 x 8 bits (M24C64) and 4096 x 8 bits
(M24C32).
nized as 8192 x 8 bits (M24C64) and 4096 x 8 bits
(M24C32).
Figure 2. Logic Diagram
I
2
C uses a two-wire serial interface, comprising a
bi-directional data line and a clock line. The devic-
es carry a built-in 4-bit Device Type Identifier code
(1010) in accordance with the I
es carry a built-in 4-bit Device Type Identifier code
(1010) in accordance with the I
2
C bus definition.
The device behaves as a slave in the I
2
C protocol,
with all memory operations synchronized by the
serial clock. Read and Write operations are initiat-
ed by a Start condition, generated by the bus mas-
ter. The Start condition is followed by a Device
Select Code and Read/Write bit (RW) (as de-
scribed in
serial clock. Read and Write operations are initiat-
ed by a Start condition, generated by the bus mas-
ter. The Start condition is followed by a Device
Select Code and Read/Write bit (RW) (as de-
scribed in
Table 3.
), terminated by an acknowl-
edge bit.
When writing data to the memory, the device in-
serts an acknowledge bit during the 9
When writing data to the memory, the device in-
serts an acknowledge bit during the 9
th
bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
Table 2. Signal Names
Power On Reset: V
CC
Lock-Out Write Protect
In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. At Power-up, the
internal reset is held active until V
Write operations during Power-up, a Power On
Reset (POR) circuit is included. At Power-up, the
internal reset is held active until V
CC
has reached
the Power On Reset (POR) threshold voltage, and
all operations are disabled – the device will not re-
spond to any command. In the same way, when
V
all operations are disabled – the device will not re-
spond to any command. In the same way, when
V
CC
drops from the operating voltage, below the
Power On Reset (POR) threshold voltage, all op-
erations are disabled and the device will not re-
spond to any command.
A stable and valid V
erations are disabled and the device will not re-
spond to any command.
A stable and valid V
CC
(as defined in
Table 9.
and
Table 10.
) must be applied before applying any
logic signal.
Figure 3. DIP, SO, TSSOP and UFDFPN
Connections
Connections
Note: See
PACKAGE MECHANICAL
section for package dimen-
sions, and how to identify pin-1.
AI01844B
3
E0-E2
SDA
VCC
M24C64
M24C32
M24C32
WC
SCL
VSS
E0, E1, E2
Chip Enable
SDA
Serial Data
SCL
Serial Clock
WC
Write Control
V
CC
Supply Voltage
V
SS
Ground
SDA
VSS
SCL
WC
E1
E0
VCC
E2
AI01845C
M24C64
M24C32
M24C32
1
2
3
4
8
7
6
5
harman/kardon
AVR 460/230 Service Manual
Page 72 of 142
Click on the first or last page to see other AVR 460 service manuals if exist.