Sony KE-37XS910 / KE-42XS910 / KE-MX37A1 / KE-MX37N1 / KE-MX37S1 Service Manual ▷ View online
– 5 –
(2) LVDS Signal Definition and Function
A video signal (display data signal and control signal) is converted from parallel data to serial
data with the LVDS transmitter and further converted into four sets of differential signals before
input to this product.
data with the LVDS transmitter and further converted into four sets of differential signals before
input to this product.
These signals are transmitted seven times faster than dot clock signals.
The dot clock signal is converted into one set of differential signals by the transmitter before
input to this product.
input to this product.
The LVDS signal definition and function are summarized below:
Signal name
Symbol
Number of
signals
Signal definition and function
RA-
RA+
1
1
1
Display data signal
R2, R3, R4, R5, R6, R7, G2
R2, R3, R4, R5, R6, R7, G2
RB-
RB+
1
1
1
Display data signal
G3, G4, G5, G6, G7, B2 B4
G3, G4, G5, G6, G7, B2 B4
RC-
RC+
1
1
1
Display data signal，Sync Signal，Control signal
B4, B5, B6, B7, Hsync , Vsync , BLANK
B4, B5, B6, B7, Hsync , Vsync , BLANK
RD-
RD+
1
1
1
Display data signal, Control signal
R8, R9, G8, G9, B8, B9, PARITY
R8, R9, G8, G9, B8, B9, PARITY
Video signal
Timing signal
Transmission line
Timing signal
Transmission line
RE-
RE+
1
1
1
Display data signal, Control signal
R0, R1, G0, G1, B0, B1, N.S
R0, R1, G0, G1, B0, B1, N.S
Clock transmission
line
line
RXCLKIN-
RXCLKIN+
1
1
1
Clock signal
DCLK
– 6 –
(3) Video Signal Definition and Function
The table below summarizes the definitions and functions of input video signals before LVDS
conversion.
conversion.
Item
Signal name
Number
of signals
Input/
output
Signal definition and function
Video signal
(digital RGB)
(digital RGB)
DATA-R
DATA-G
DATA-B
DATA-G
DATA-B
10
10
10
10
10
Input
Display data signal
R9/G9/B9 is the highest intensity bit.
R0/G0/B0 is the lowest intensity bit.
R9/G9/B9 is the highest intensity bit.
R0/G0/B0 is the lowest intensity bit.
Data Clock
DCLK
１
Input
Display data timing signal: Data are read when
DCLK is lowerd. DCLK is continuously
input.
Horizontal
sync signal
sync signal
Hsync
1 Input
Regulates one horizontal line of data: Begins
control of the next screen when Hsync is
lowered.
control of the next screen when Hsync is
lowered.
Vertical sync
signal
signal
Vsync
1 Input
Screen starts up control timing signal: Begins
control of the next screen when Vsync is
lowered.
Input the same frequency in both
odd-numbered and even-numbered fields.
control of the next screen when Vsync is
lowered.
Input the same frequency in both
odd-numbered and even-numbered fields.
Parity signal
PARITY
1
Input
This signal specifies the display field.
H: Odd-numbered field
L: Even-numbered field
Parity signal should be alternated in every
H: Odd-numbered field
L: Even-numbered field
Parity signal should be alternated in every
Vsync cycle.
Original
Display signal
(before LVDS
transmittance)
Display signal
(before LVDS
transmittance)
Blanking
signal
signal
BLANK
1 Input
Display period timing signal.
H indicates the display period and L indicates
the non display period.
Note:
Set this timing properly like followings, as is
used internally for signal processing.
H indicates the display period and L indicates
the non display period.
Note:
Set this timing properly like followings, as is
used internally for signal processing.
・
Set the blanking period so that the number of
effective display data items in one horizontal
period is 1024.
effective display data items in one horizontal
period is 1024.
・
Set the number of blanking signals in one
vertical period to 512, which is one half the
number of effective scan lines.
number of effective scan lines.
If the BLANK changes when the Vsync
frequency is switched, the screen display may
be disturbed or brightness may change.
The screen display is restored to the normal
state later when the BLANK length is
constant again.
frequency is switched, the screen display may
be disturbed or brightness may change.
The screen display is restored to the normal
state later when the BLANK length is
constant again.
*This product does not correspond to the progressive display mode by the parity signal fixation.
When the parity signal is fixed, this product is reversed arbitrarily internally and used.
– 7 –
1.3.4
Connector Specifications
The connector specification is shown below. Please do not connect anything with the terminal
NC.
NC.
(1) Signal connector [CN1]
Pin No.
Signal name
Pin No.
Signal name
1 RA- 2
GND(LVDS)
3 RA+ 4 SCL
5 RB- 6 GND
7 RB+ 8 SDA
9 RC- 10
GND(LVDS)
11 RC+ 12
CPUGO
13 RXCLKIN- 14 PDPGO
15 RXCLKIN+ 16
IRQ
17 RD- 18
PDWN
19 RD+ 20
GND(LVDS)
21 RE- 22 GND
23 RE+ 24 GND
25 GND 26 GND
27 GND 28 GND
29 GND 30 GND
DF13-30DP-1.25 V (tin-plated) (Maker: HIROSE DENKI)
[Conforming connector] Housing: DF13-30DS-1.25C
Contact: DF13-2630SCF
(2) Power Source Connectors (PSU only is used on repair working)
(a) Power input connector [CN61]
Pin No.
Symbol
1 AC(L)
2 N.C
3 AC(N)
4 N.C
5 N.C
6 F.G
B06P-VH (Maker: JST)
[Conforming connector]
Housing: VHR-06N(or M)
Contact: SVH-21T-P1.1
Contact: SVH-21T-P1.1
– 8 –
(b) Power supply output connector for system [CN62]
Pin No.
Symbol
1 V
AUX
2 N.C
3 GND
B03P-VH (Maker: JST)
[Conforming connector]
Housing: VHR-06N(or M)
Contact: SVH-21T-P1.1
Contact: SVH-21T-P1.1
(c) Power supply output connector for system [CN63]
Pin No.
Symbol
1 Vpr1
2 N.C.
3 Vpr2
4 N.C.
5 GND
B5B-XH-A (Maker: JST)
[
Conforming connector]
Housing: XHP-5
Contact: SXH-001T-P0.6
Contact: SXH-001T-P0.6
(iii) Power Source Connectors
(a) Power supply output connector for system [CN6]
Pin No.
Symbol
1 Vpr2
2 N.C.
3 GND
4 GND
5 N.C.
6 Vcc
B6B-PH-SM3(JST)
[Conforming connector]
Housing: PHR-6
Contact: SPH-002T-P0.5L
Contact: SPH-002T-P0.5L
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