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– 13 –

 

3.2.2 

Power Diagrams 

 

Y-SCAN 

EVEN SW

 

X-SCAN 

EVEN SW 

ABUSR B....    

．

．

．

．

 

 

 

B 

 

 

 

M 

 

 

Y-SUS B. 

X-SUS B. 

LOGIC B. 

ADM1 

Y-SUS  

EVEN SW

 

X-SUS  

EVEN SW

 

Y-SUS  

ODD SW

 

Y-SCAN  

ODD SW

 

X-SUS  

ODD SW

 

X-SCAN  

ODD SW

 

POS/NEG  

RESET SW

 

DC/DC 

CONVERTER 

     
Vx

    

55V

 

Vs 85V 

PFC 

Vs

Va

5/3.3V

control

 

Vcc

MPU 

380V

 

PFCgo 

Vsago 

Vcego

Vsago 

Vsago 

Vcego 

PFCgo 

10A 

CPUgo 
PDPgo

 

CN23

 

5V

 

63V

 

AC100 

~240V 

Vxwgo 

DC/DC 

CONVERTER 

    X

FVE

        Vxx

 

        VE 

    18V                20V          17V 

Vcc 5V 

DC/DC 

CONVERTER 

 

YFVE  Vy  VE 

  18V  18V 17V 

Vcc 5V 
Vs 85V 
Va 63V 
Vw  190V 
Vu  55V 

V

pr2  3.3V

 

Vs 
85V 

Servce 

SW 

POS/NEG  

RESET SW

 

Vrst 

Vcc 5V 

Vpr2 3.3V 

85V

 

Vcc 5V 

Vcc 5V 

Va 63V 

Va 63V 

V

pr1      5V

 

RST 

CN32

 

CN22

 

CN42

 

CN52

 

CN6

 

CN61

 

CN64

 

CN68

 

D/A 

V

ra  

Vra
Vrs
Vrw
Vrx

PSU B. 

ADM4 

ADM2 

ADM5

 

ADM3 

ADM6  ADM7  ADM8 

Vcc 5V 
Vs 85V 
Va 63V 

CN26

 

CN36

 

– 14 –

 

3.3.1 

Logic board Function   

(1) Data Processor 

- γ adjustment(1 / 2.2 / 2.4 / 2.6 / 2.8) 
- NTSC/EBU format(Color matrix) Switch 
- RGB gain Control(White balance adjustment, Amplitude limitation) 
- Error Diffusion Technology(Grayscale adjustment) 
- Dither(Grayscale adjustment) 
- Burn-in Pattern generation 

 

(2) Data Converter 

- Quasi out-line adjustment (luminous pattern control) 

 

(3) Scan Controller 

- Address driver control signal generator(ADM) 
- scan driver control signal generator(SDM) 
- X/Y sustain control signal generator 

 

(4) Waveform ROM 

- Waveform Pattern for drive / Timing memory 

 

(5) MPU 

- Synchronous detection 
- System control 
- Driving voltage(Va, Vs, Vr, Vw) Minute adjustment 
- Abnormal watch (breakdown detection)/abnormal processing 
- Is(sustain) current control (sustain pulse control) 
- Ia(address) current control (sub-field control) 
- External communication control 
- Flash memory (firmware) 

 

(6) EEPROM 

- Control parameter memory 
- The accumulation energizing time (Every hour). 
- Abnormal status memory (16 careers) 

 

 

 

 

 

 

 

 

– 15 –

 

00 7-0 

MAPVER 

address MAP 
VERsion 

Indicates the version number of the 
address map. 

00 ~ FF 

01 

7 ERRF 

update of 
ERRor Flag 

Indicates that an error has occurred. 
It can be cleared with the ErrRST 
setting.  
If this flag is set, Error code is 
written. Cannot enter the PDP-ON 
mode. 

0: Not updated 

1: Updated 

0 

6 OHRF 

update of 
Operation 
HouRs Flag   

Indicates that the drive hours are 
counted.  

0: Not updated 

1: Updated 

0 

5 PSDF 

Power Shut 

Down Flag 

Indicates that shutdown of the AC 
power is detected and the PDP has 
executed the OFF-sequence. It can 
be cleared with the PSDRST setting.   

0: Not detected 

1: Detected 

0 

01 

4-0 CNDC 

CoNDition 
Code 

Indicates status of the module. 

Refer to 4.11.2.6 
condition codes. 

Irregular 

02 7-0 

ERRC 

  ERRor 

Code 

Indicates error code. 
The error codes of as many as 16 
errors in the past can be retrieved 
with the ERRS setting. 

.

 

Same error 

code is not stored continuously.

 

00~FF 00 

03 7-0 

OHRH 

Operation 
HouRs 
Higher bits 

Indicates the higher 8 bits of the 
module driving hours.   

00~FF 00 

04 7-0 

OHRL 

Operation 
HouRs Lower 
bits 

Indicates the lower 8 bits of the 
module driving hours.   

00~FF 00 

 

 

 

 

 

 

 

 

– 16 –

 

7 PATSEL 

Selecting 
patterns 

It selects the built-in test pattern 
signals of this display. This setting is 
valid when the PATON setting is 1. 

0: The single color 

display is switched 
every 2 seconds. A 
total of 8 colors are 
displayed. 

1:All white (Different 

from actual white.) 

0 

6 PATON 

Built-in 
pattern 
display is set 
to ON.   

Display of the built-in pattern signal 
in this product is turned ON/OFF. 

0: Displaying the 

input signal 

1: Displaying the 

built-in pattern 

0 

5 ADEN 

Address 
data enable 

The black screen is displayed. 

0 is set when the input video signal 
has disturbance. 

0: Blank 

1: Displaying the 

input signal 

1 

4 

- 

- 

Be sure to use the display with the 
setting fixed to 0. 

0~1 0 

3 

DSPPOL 

DiSPlay 
POLarity 

Input reflection polarity setting 

0:Emits light by LOW 

1:Emits light by High 

1  

2 PFCON 

forcing PFC 
ON 

When PFCON = 0, If a high voltage 
power is switched on, PFCGO is set 
high before a high voltage power is 
output.  
When PDPON = 1, PFCGO is set 
high irrespective of the state of a 
high voltage power. 
Use it for a power control when a 
high voltage power is off. 

0: Power OFF 

1: Power ON 

0 

1 PDPON 

High voltage 
power supply 

ON 

Switches ON/OFF the high voltage 
power supply of PDP. 

0: Power OFF 

1: Power ON 

0 

20 

0 

DSPBIT 

Input Data bit  Switches 8 bit input / 10 bit input 

0: 10 bit input 

1:  8bit input 

1