Sony XES-Z50 (serv.man4) Service Manual ▷ View online
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CHANGER BOARD IC301 CXP846P48Q-1-004 (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Function
1
LED
O
LED drive signal output for the eject indicator “L”: LED on
2
—
O
Not used (open)
3
—
O
Not used (open)
4
EECLK
O
Serial data transfer clock signal output to the EEPROM (IC302)
5
SINGLE
I
Input terminal for setting CD single mode or CD changer mode
“L”: CD single mode, “H”: CD changer mode (fixed at “H”)
“L”: CD single mode, “H”: CD changer mode (fixed at “H”)
6
MC
O
Elevator up/down motor (M501) and disc load/save motor (M502) drive signal output to the
BA6247FP (IC201) *1
BA6247FP (IC201) *1
7
MB
O
Elevator up/down motor (M501) drive signal output to the BA6247FP (IC201) *1
8
MA
O
Disc load/save motor (M502) drive signal output to the BA6247FP (IC201) *1
9
PGR
O
Plunger drive signal output for the magazine out
10
M3
O
Disc eject motor (M801) drive signal output to the BA6287F (IC801)
11
M3
O
Disc eject motor (M801) drive signal output to the BA6287F (IC801)
12
ELVON
O
Output of power on/off control signal for the CD section main power supply “H”: power on
13
CDRST
O
Reset signal output to the D-RAM controller (IC401), digital signal processor (IC501), and digital
servo processor (IC601) “L”: reset
servo processor (IC601) “L”: reset
14
XTLSEL
O
Output terminal for setting DSP crystal “H”: internal clock, “L”: external clock
Not used (open)
Not used (open)
15
APC
O
Laser diode on/off control signal output to the RF amplifier (IC101) “L”: laser on
16
DPT
I
Detection input from the disc detect sensor (Q702) Whether a disc is present at the reset
processing or load/save processing is detected (“L” is input while a disc is fed)
processing or load/save processing is detected (“L” is input while a disc is fed)
17
DOE
I
Detection input from the disc detect sensor (Q701) Whether a disc is present at the reset
processing or load processing is detected (“L” is input when a disc is above the pickup)
processing or load processing is detected (“L” is input when a disc is above the pickup)
18
CES
I
Detection input from the disc chucking completion detect switch (SW701)
“L” is input when disc chucking is completed
“L” is input when disc chucking is completed
19
HOME
I
Detection input from the home/top position detect switch (SW501)
“L” is input when elevator is at the home position
“L” is input when elevator is at the home position
20
PST
I
Detection input from the magazine detect switch (SW804) “L”: magazine in
21
LOT
I
Detection input from the liner slide lever position detect switch (SW803) “L”: magazine in
22
XWRE
O
Enable signal output for data writing to the D-RAM controller (IC401)
23
XRDE
O
Enable signal output for data reading to the D-RAM controller (IC401)
24
XQOK
O
Output of definite subcode Q data to the D-RAM controller (IC401)
25
GRSRST
O
Reset signal output to the D-RAM controller (IC401) At track jump, “H” is output
26
ESPXLT
O
Serial latch signal output to the D-RAM controller (IC401)
27
XSOE
O
Enable signal output for data reading to the D-RAM controller (IC401)
28
SDTI
I
Serial data input from the D-RAM controller (IC401)
29
—
O
Not used (open)
30
RESET
I
System reset signal input from the reset signal generator (IC903) and bus interface (IC951) (for
SONY bus) “L”: reset For several hundreds msec. after the power supply rises, “L” is input,
then it changes to “H”
SONY bus) “L”: reset For several hundreds msec. after the power supply rises, “L” is input,
then it changes to “H”
*1 Elevator up/down motor, disc load/save motor control
Elevator up
Elevator down
Disc load
Disc save
MA (pin 8)
“L”
“H”
“L”
“H”
MB (pin 7)
“L”
“L”
“H”
“H”
MC (pin 6)
“H”
“H”
“L”
“L”
Terminal
Operation
Disc load/save motor (M502)
Elevator up/down motor (M501)
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Pin No.
Pin Name
I/O
Function
31
XTLI
I
Main system clock input terminal (8 MHz)
32
XTLO
O
Main system clock output terminal (8 MHz)
33
VSS
—
Ground terminal
34
TX
O
Sub system clock output terminal (32.768 kHz) Not used (open)
35
TEX
I
Sub system clock input terminal (32.768 kHz) Not used (fixed at “L”)
36
AVSS
—
Ground terminal (for A/D conversion)
37
AVREF
I
Reference voltage input terminal (+5V) (for A/D conversion)
38
TEMP H
I
Temperature detect thermistor (TH301) input terminal (A/D input)
Used for high temperature detection data input (for servo gain compensation)
Used for high temperature detection data input (for servo gain compensation)
39
TEMP L
I
Temperature detect thermistor (TH302) input terminal (A/D input)
Used for low temperature detection data input (for servo gain compensation)
Used for low temperature detection data input (for servo gain compensation)
40
SEL
O
Not used (open)
41
TEMP D
I
Input of temperature compensation inhibit “L”: inhibit (fixed at “H”)
42
—
O
Not used (open)
43
RSTO
O
Reset signal output to the CD text decoder (IC303) “L”: reset
44
BUSY
I
Busy signal input from the CD text decoder (IC303)
45
REQ
I
Request signal input from the CD text decoder (IC303)
46
GRSCOR
I
Subcode sync detection signal input from the D-RAM controller (IC401)
47
EEDATA
I/O
Two-way data bus with the EEPROM (IC302)
48
CCLK
O
Serial data transfer clock signal output to the CD text decoder (IC303)
49
CSO
O
Serial data output to the CD text decoder (IC303)
50
CSI
I
Serial data input from the CD text decoder (IC303)
51
SCK
I
Serial data transfer clock signal input from the bus interface (IC951) (for SONY bus)
52
SI
I
Serial data input from the bus interface (IC951) (for SONY bus)
53
SO
O
Serial data output to the bus interface (IC951) (for SONY bus)
54
BUSON
I
Bus on/off control signal input from the bus interface (IC951) (for SONY bus)
“L”: bus on (used also to reset standby)
“L”: bus on (used also to reset standby)
55
EJTKEY
I
Eject switch (SW11) input terminal
56
SCOR
I
Subcode sync (S0+S1) detection signal input from the digital signal processor (IC501)
57
EEINIT
I
Initial reset input of the EEPROM “L”: initial reset (fixed at “L”)
58
—
O
Not used (open)
59
—
O
Not used (open)
60
WUP
I
Key wake-up input terminal In this set, the signal from EJECT switch (SW11) and bus on signal
from the bus interface (IC951) (for SONY bus) are input
from the bus interface (IC951) (for SONY bus) are input
61
LOCK
I
Detection input from the magazine lock detect switch (SW802) “H”: magazine lock
62
EHS
I
Elevator height detection signal input terminal
63
OPEN
I
Detection input from the door open/close detect switch (SW12)
“H”: door open, “L”: door close
“H”: door open, “L”: door close
64
B.U.CHECK
I
Backup power supply detection signal input terminal (used also to reset standby)
65
SQCK
O
Clock signal output for subcode Q data reading to the digital signal processor (IC501)
66
SUBQ
I
Subcode Q data input from the digital signal processor (IC501)
67
—
O
Not used (open)
68
CDCLK
O
Serial data transfer clock signal output to the D-RAM controller (IC401) and digital signal
processor (IC501)
processor (IC501)
69
CDXLT
O
Serial latch signal output to the digital signal processor (IC501)
70
CDDATA
O
Serial data output to the D-RAM controller (IC401) and digital signal processor (IC501)
71
SCLK
O
Clock signal output for SENS serial data reading to the digital servo processor (IC601)
72
VDD
—
Power supply terminal (+5V)
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Pin No.
Pin Name
I/O
Function
73
NC
I
Not used (fixed at “H”)
74
A-MUTE
O
Audio mute on/off control signal output terminal “H”: mute Not used (open)
75
FOK
I
Focus OK signal input from the digital servo processor (IC601) “L”: NG, “H”: OK
76
GFS
I
Guard frame sync signal input from the digital signal processor (IC501) “L”: NG, “H”: OK
77
SENS
I
Count sense signal input from the digital signal processor (IC501)
78
—
O
79
—
O
Not used (open)
80
—
O
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CHANGER BOARD IC303 CXP83413-035Q (CD TEXT DECODER)
Pin No.
Pin Name
I/O
Function
1
NC
O
Not used (open)
2
NC
O
Not used (open)
3
NC
I
Not used (fixed at “L”)
4
REQ
O
Request signal output to the system controller (IC301)
5
CCLK
I
Serial data transfer clock signal input from the system controller (IC301)
6
CSI
I
Serial data input from the system controller (IC301)
7
CSO
O
Serial data output to the system controller (IC301)
8
SCLK
O
Clock signal output for subcode data reading to the digital signal processor (IC501)
9
SSI
I
Subcode data input from the digital signal processor (IC501)
10
NC
O
Not used (open)
11
ADD0
O
12
ADD1
O
13
ADD2
O
14
ADD3
O
15
ADD4
O
16
ADD5
O
17
ADD6
O
18
ADD7
O
19
RAMSEL
I
Not used (open)
20
DATA0
I/O
21
DATA1
I/O
22
DATA2
I/O
23
DATA3
I/O
24
DATA4
I/O
25
DATA5
I/O
26
DATA6
I/O
27
DATA7
I/O
28
RST
I
System reset signal input from the system controller (IC301), reset signal generator (IC903), and
bus interface (IC951) (for SONY bus) “L”: reset For several hundreds msec. after the power
supply rises, “L” is input, then it changes to “H”
bus interface (IC951) (for SONY bus) “L”: reset For several hundreds msec. after the power
supply rises, “L” is input, then it changes to “H”
29
EXTAL
I
System clock input terminal (10 MHz)
30
XTAL
O
System clock output terminal (10 MHz)
31
VSS
—
Ground terminal
32 to 55
NC
O
Not used (open)
56
BUSY
O
Busy signal output to the system controller (IC301)
57 to 59
NC
O
Not used (open)
60
ADD16
O
Address signal output to the S-RAM (IC304)
61
NC
O
Not used (open)
62
CE
O
Chip enable signal output to the S-RAM (IC304)
63
WE
O
Write enable signal output to the S-RAM (IC304)
64
ADD8
O
65
ADD9
O
66
ADD10
O
67
ADD11
O
68
ADD12
O
69
ADD13
O
Address signal output to the S-RAM (IC304)
Two-way data bus with the S-RAM (IC304)
Address signal output to the S-RAM (IC304)
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