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– 45 –

Pin No.

Pin Name

I/O

Function

70

VDD

—

Power supply terminal (+5V)

71

NC

O

Not used (open)

72

NC

I

Not used (fixed at “L”)

73

NC

I

Not used (fixed at “H”)

74

ADD14

O

Address signal output to the S-RAM (IC304)

75

ADD15

O

Address signal output to the S-RAM (IC304)

76

SCOR

I

Subcode sync (S0+S1) detection signal input from the digital signal processor (IC501)

77

WFCK

I

Write frame clock (7.35 kHz) signal input from the digital signal processor (IC501)

78

BUCK

I

Backup power supply detection signal input terminal (used also to reset standby)

79

NC

I

Not used (fixed at “L”)

80

NC

I

Not used (fixed at “L”)

– 46 –

•

Pin No.

Pin Name

I/O

Function

1

VSS

—

Ground terminal

2

CRDY

O

Output of ready signal at serial data transfer to the master controller (IC301)                                    
The start cause interruption occurs by a falling edge

3

CCNT

I

Input of control/data from address bus for the master controller (IC301)    “L”: data input

4

XCWR

I

Strobe signal input for data writing from the master controller (IC301)                                             
Data are written by a falling edge

5

XCRD

I

Strobe signal input for data reading from the master controller (IC301)    “L”: data read

6

VDD

—

Power supply terminal (+3.3V)

7

CD0

I/O

Two-way data bus (LSB) with the master controller (IC301)

8

CD1

I/O

9

CD2

I/O

Two-way data bus with the master controller (IC301)

10

CD3

I/O

11

VSS

—

Ground terminal

12

CD4

I/O

13

CD5

I/O

Two-way data bus with the master controller (IC301)

14

CD6

I/O

15

CD7

I/O

Two-way data bus (MSB) with the master controller (IC301)

16

VDD

—

Power supply terminal (+3.3V)

17

MUTE

I

Mute control signal input of the audio data    “L”: mute    Not used (fixed at “H”)

18

CCS

I

Input of chip select signal from address bus for the master controller (IC301)

19

VSS

—

Ground terminal

20

MCKO

O

Master clock signal (18.432 MHz) output terminal    Not used (open)

21

VSS

—

Ground terminal

22

XTO

O

System clock signal (33.8688 MHz) output terminal    Not used (open)

23

XTI

I

System clock signal (33.8688 MHz) input terminal

24

VSS

—

Ground terminal

25

(BIST)

O

Output terminal for the test    Not used (open)

26

(TCK)

O

Output terminal for the test    Not used (open)

27

(TDI)

O

Output terminal for the test    Not used (open)

28

(TENA1)

O

Output terminal for the test    Not used (open)

29

(TDO)

O

Output terminal for the test    Not used (open)

30

(VST)

I

Input terminal for the test    Not used (fixed at “L”)

31

VSS

—

Ground terminal

32

RESET

I

Reset signal input from the master controller (IC301)    “L”: reset

33

BCLK

O

Block clock signal output terminal    Not used (open)

34

LRCK

I

L/R sampling clock signal (44.1 kHz) input of the serial in/out data

35

BCK

I

Bit clock signal (2.8224 MHz) input of the serial in/out data

36

VSS

—

Ground terminal

37

SIA

I

38

SIB

I

Serial audio data input terminal
IC101: Serial data (for front speaker) input from the CXD2710R (IC601)
IC201: Serial data (for sub-woofer speaker) input from the CXD2710R (IC601)

Serial audio data input terminal
IC101: Serial data (for rear speaker) input from the CXD2710R (IC601)
IC201: Not used (fixed at “L”)

– 47 –

Pin No.

Pin Name

I/O

Function

39

SOA

O

40

SOB

O

41

VSS

—

Ground terminal

42

TST1

I

Input terminal for the test    Not used (fixed at “L”)

43

TST2

I

Input terminal for the test    Not used (fixed at “L”)

44

TST3

I

Input terminal for the test    Not used (fixed at “L”)

45

TST4

I

Input terminal for the test    Not used (fixed at “L”)

46

VDD

—

Power supply terminal (+3.3V)

47

TST5

I

Input terminal for the test    Not used (fixed at “L”)

48

TST6

I

Input terminal for the test    Not used (fixed at “L”)

49

VSS

—

Ground terminal

50

MD00

I/O

51

VSS

—

Ground terminal

52

MD01

I/O

53

MD02

I/O

54

MD03

I/O

55

VSS

—

Ground terminal

56

MD04

I/O

57

MD05

I/O

58

MD06

I/O

59

MD07

I/O

60

VDD

—

Power supply terminal (+3.3V)

61

VSS

—

Ground terminal

62

MD08

I/O

63

MD09

I/O

64

MD10

I/O

65

MD11

I/O

66

VDD

—

Power supply terminal (+3.3V)

67

MD12

I/O

68

MD13

I/O

69

MD14

I/O

70

MD15

I/O

71

VSS

—

Ground terminal

72

RAS

O

73

MA09

O

74

MA10

O

Address signal output terminal    Not used (open)

75

MA11

O

76

VDD

—

Power supply terminal (+3.3V)

77

MA12

O

Address signal output terminal    Not used (open)

Serial audio data output terminal
IC101: Serial data (for front speaker) output terminal
IC201: Serial data (for sub-woofer speaker) output terminal

Serial audio data output terminal
IC101: Serial data (for rear speaker) output terminal
IC201: Not used (open)

IC101: Two-way data bus with the D-RAM (IC102)
IC201: Two-way data bus with the D-RAM (IC202)

IC101: Two-way data bus (LSB) with the D-RAM (IC102)
IC201: Two-way data bus (LSB) with the D-RAM (IC202)

IC101: Two-way data bus with the D-RAM (IC102)
IC201: Two-way data bus with the D-RAM (IC202)

IC101: Two-way data bus with the D-RAM (IC102)
IC201: Two-way data bus with the D-RAM (IC202)

IC101: Two-way data bus with the D-RAM (IC102)
IC201: Two-way data bus with the D-RAM (IC202)

IC101: Two-way data bus (MSB) with the D-RAM (IC102)
IC201: Two-way data bus (MSB) with the D-RAM (IC202)

IC101: Row address strobe signal output to the D-RAM (IC102)
IC201: Row address strobe signal output to the D-RAM (IC202)

– 48 –

Pin No.

Pin Name

I/O

Function

78

MA13

O

79

MA14

O

Address signal output terminal    Not used (open)

80

MA15

O

81

VSS

—

Ground terminal

82

MA00

O

83

MA01

O

84

VSS

—

Ground terminal

85

MA02

O

86

MA03

O

87

VDD

—

Power supply terminal (+3.3V)

88

MA04

O

89

MA05

O

90

VSS

—

Ground terminal

91

VSS

—

Ground terminal

92

MA06

O

93

MA07

O

94

VSS

—

Ground terminal

95

MA08

O

96

MA16

O

Address signal output terminal    Not used (open)

97

MA17

O

Address signal output terminal    Not used (open)

98

VDD

—

Power supply terminal (+3.3V)

99

WE

O

100

OE

O

101

VSS

—

Ground terminal

102

ROM-CE

O

Chip enable signal output terminal    Not used (open)

103

CAS

O

104

VSS

—

Ground terminal

105

DEND

O

Internal operation monitor output terminal    Not used (open)

106

VDD

—

Power supply terminal (+3.3V)

107

PEND

O

Internal operation monitor output terminal    Not used (open)

108

ENC0

O

109

ENC1

O

Internal operation monitor output terminal    Not used (open)

110

ENC2

O

111

VSS

—

Ground terminal

112

STOP

O

Internal operation monitor output terminal    Not used (open)

113

HOLD

O

Internal operation monitor output terminal    Not used (open)

114

OVF

O

Overflow monitor output terminal at the operation    “H”: overflow    Not used (open)

115

LIM

O

Fixed/float conversion limiter output terminal    “H”: limiter on    Not used (open)

116

BTIA

I

Bit input terminal    Not used (fixed at “L”)

117

BTIB

I

Bit input terminal    Not used (fixed at “L”)

118

BTOA

O

Bit output terminal    Not used (open)

119

BTOB

O

Bit output terminal    Not used (open)

120

VDD

—

Power supply terminal (+3.3V)

IC101: Address signal output to the D-RAM (IC102)
IC201: Address signal output to the D-RAM (IC202)

IC101: Address signal output to the D-RAM (IC102)
IC201: Address signal output to the D-RAM (IC202)

IC101: Address signal output to the D-RAM (IC102)
IC201: Address signal output to the D-RAM (IC202)

IC101: Address signal output to the D-RAM (IC102)
IC201: Address signal output to the D-RAM (IC202)

IC101: Address signal output to the D-RAM (IC102)
IC201: Address signal output to the D-RAM (IC202)

IC101: Write enable signal output to the D-RAM (IC102)
IC201: Write enable signal output to the D-RAM (IC202)

IC101: Output enable signal output to the D-RAM (IC102)
IC201: Output enable signal output to the D-RAM (IC202)

IC101: Column address strobe signal output to the D-RAM (IC102)
IC201: Column address strobe signal output to the D-RAM (IC202)