Sony XES-Z50 (serv.man4) Service Manual ▷ View online
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DSP BOARD IC301 HD6473048SF16-DSP01 (MASTER CONTROLLER)
Pin No.
Pin Name
I/O
Function
1
VDD
—
Power supply terminal (+5V)
2
PW-ON
O
Output of power on/off control signal for the system power supply (digital/analog power supply,
amp remote etc.) “H”: power on
amp remote etc.) “H”: power on
3
S-OUT
O
Serial data output to the EEPROM (IC302), input selector (IC415), digital signal processor
(IC601 CXD2710R), and electrical volume (IC1106, 1206, 1306)
(IC601 CXD2710R), and electrical volume (IC1106, 1206, 1306)
4
S-CKO
O
Serial data transfer clock signal output to the input selector (IC415), digital signal processor
(IC601 CXD2710R), and electrical volume (IC1106, 1206, 1306)
(IC601 CXD2710R), and electrical volume (IC1106, 1206, 1306)
5
DSPRST
O
Reset signal output to the digital signal processor (IC101, 201 CXD2711Q/IC601 CXD2710R),
and digital filter (IC1101, 1201, 1301) “L”: reset
and digital filter (IC1101, 1201, 1301) “L”: reset
6
2710-CE
O
Chip enable signal output to the digital signal processor (IC601 CXD2710R)
7
EE-CKO
O
Serial data transfer clock signal output to the EEPROM (IC302)
8
SP-CE
O
Chip enable signal output to the input selector (IC415)
9
DSP-RDY
I
Input of ready signal at data transfer from the digital signal processor (IC101, 201 CXD2711Q)
The start cause interruption occurs by a falling edge
The start cause interruption occurs by a falling edge
10
VPP
I
Not used (fixed at “L”)
11
GND
—
Ground terminal
12
S-OUT (TX)
O
UART (Universal Asynchronous Receiver/Transmitter) transmit output of the master bus
controller (CN12)
controller (CN12)
13
UNISO
O
Serial data output to the bus interface (IC306) (for SONY bus)
14
S-IN (RX)
I
UART (Universal Asynchronous Receiver/Transmitter) receive input of the master bus controller
(CN12)
(CN12)
15
UNISI
I
Serial data input from the bus interface (IC306) (for SONY bus)
16
NIL
I
Not used (fixed at “L”)
17
UNICKI
I
Serial data transfer clock signal input from the bus interface (IC306) (for SONY bus)
18
D0
I/O
19
D1
I/O
20
D2
I/O
21
D3
I/O
22
VSS
—
Ground terminal
23
D4
I/O
24
D5
I/O
25
D6
I/O
26
D7
I/O
27
D8
I/O
28
D9
I/O
29
D10
I/O
30
D11
I/O
31
D12
I/O
32
D13
I/O
33
D14
I/O
34
D15
I/O
35
VDD
—
Power supply terminal (+5V)
36
A0
O
Address signal output terminal In this set, the chip enable signal output to the digital signal
processor (IC101 CXD2711Q)
processor (IC101 CXD2711Q)
37
A1
O
Address signal output to the flash memory (IC401, 402), and chip enable signal output to the
digital signal processor (IC201 CXD2711Q)
digital signal processor (IC201 CXD2711Q)
38
A2
O
39
A3
O
Two-way data bus with the flash memory (IC401)
Two-way data bus with the flash memory (IC401)
Two-way data bus with the digital signal processor (IC101, 201 CXD2711Q) and flash
memory (IC402)
memory (IC402)
Address signal output to the flash memory (IC401, 402)
– 50 –
Pin No.
Pin Name
I/O
Function
40
A4
O
41
A5
O
42
A6
O
43
A7
O
44
VSS
—
Ground terminal
45
A8
O
46
A9
O
47
A10
O
48
A11
O
49
A12
O
50
A13
O
51
A14
O
52
A15
O
53
A16
O
54
A17
O
55
A18
O
56
A19
O
57
VSS
—
Ground terminal
58
MUTE
O
Relay drive signal output for the speaker protect relay (RY1101, 1201, 1301)
At output of “L”, the relay is turned on to apply muting
At output of “L”, the relay is turned on to apply muting
59
SMUTE
O
Soft mute control signal output to the electrical volume (IC1106, 1206, 1306) “H”: mute on
60
EMP-O
O
Emphasis control signal output to the digital filter (IC1101, 1201, 1301) “H”: emphasis on
61
NCO
O
System clock signal output terminal Not used (open)
62
STBY
I
Standby signal input terminal Fixed at “H” in this set
63
SYSRES
I
System reset signal input from the reset signal generator (IC303) and bus interface (IC306) (for
SONY bus) “L”: reset For several hundreds msec. after the power supply rises, “L” is input,
then it changes to “H”
SONY bus) “L”: reset For several hundreds msec. after the power supply rises, “L” is input,
then it changes to “H”
64
BU-IN
I
Backup power supply detect signal input terminal (used also to reset standby)
65
VSS
—
Ground terminal
66
X-IN
I
System clock input terminal (14.74 MHz)
67
EX-IN
I
System clock input terminal (14.74 MHz)
68
VDD
—
Power supply terminal (+5V)
69
AS
O
Address strobe signal output terminal Not used (open)
70
RD
O
Strobe signal output for data reading to the digital signal processor (IC101, 201 CXD2711Q) and
flash memory (IC401, 402)
flash memory (IC401, 402)
71
HWR
O
Strobe signal output for upper byte data writing to the digital signal processor (IC101, 201
CXD2711Q) and flash memory (IC402)
CXD2711Q) and flash memory (IC402)
72
LWR
O
Strobe signal output for lower byte data writing to the flash memory (IC401)
73
MD0
I
Input terminal for setting microcomputer operation mode (fixed at “L”)
74
MD1
I
Input terminal for setting microcomputer operation mode (fixed at “H”)
75
MD2
I
Input terminal for setting microcomputer operation mode (fixed at “H”)
76
AVDD
—
Power supply terminal (+5V) (for A/D conversion)
77
AVREF
I
Reference voltage input terminal (+5V) (for A/D conversion)
78
NIH
I
Fixed at “H” in this set
79
DIR-ERR
I
PLL unlock error detection signal input from the digital audio interface receiver (IC502)
“H”: error
“H”: error
80
EMP-IN
I
Emphasis detection signal input from the digital signal processor (IC501 CXD2540Q) and digital
audio interface receiver (IC502) “H”: emphasis on
audio interface receiver (IC502) “H”: emphasis on
81
VOLMAX
I
Input terminal for the test mode Not used (fixed at “L”)
Address signal output to the flash memory (IC401, 402)
Address signal output to the flash memory (IC401, 402)
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Pin No.
Pin Name
I/O
Function
82
DSP-BUSY
I
Input of busy signal at serial data transfer from the digital signal processor (IC601 CXD2710R)
83
DSP-PLL
I
Not used (fixed at “L”)
84
BU-IN
I
Backup power supply detection signal input terminal (used also to reset standby)
85
DSP-SI
I
Serial data input from the digital signal processor (IC601 CXD2710R)
86
AVSS
—
Ground terminal (for A/D conversion)
87
BUS-ON
I
Bus on/off control signal input from the bus interface (IC306) (for SONY bus) “L”: bus on
With the bus in off status, standby is cancelled by bus on falling edge
With the bus in off status, standby is cancelled by bus on falling edge
88
2711-CE
O
Chip enable signal output to the digital signal processor (IC101, 201 CXD2711Q)
89
FROM-CE2
O
Chip enable signal output to the flash memory (IC401, 402)
90
FROM-CE1
O
Chip enable signal output to the flash memory (IC401, 402)
91
BOOT
I
Input of forced boot mode detection At the reset, if “H” is entered, the boot mode is forcibly
activated
activated
92
VSS
—
Ground terminal
93
LINKOFF1
O
Bus on/off control signal output to the bus interface (IC951) (for SONY bus) “L”: bus on
94
TEND
O
Not used (open)
95
LINKOFF2
O
Bus on/off control signal output for the AUX bus control “L”: bus on
96
LINKOFF3
O
Bus on/off control signal output terminal “L”: bus on Not used (open)
97
VOLCE0
O
Chip enable signal output to the electrical volume (IC1106) (for front speaker)
98
VOLCE1
O
Chip enable signal output to the electrical volume (IC1206) (for rear speaker)
99
VOLCE2
O
Chip enable signal output to the electrical volume (IC1306) (for sub-woofer speaker)
100
A20
O
Address signal output to the flash memory (IC401, 402), and control/data output to the digital
signal processor (IC101, 201 CXD2711Q)
signal processor (IC101, 201 CXD2711Q)
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DSP BOARD IC601 CXD2710R (DIGITAL SIGNAL PROCESSOR)
Pin No.
Pin Name
I/O
Function
1
AMPIN
I
Loop filter amplifier input for the PLL Not used (fixed at “L”)
2
AMPOUT
O
Loop filter amplifier output for the PLL Not used (open)
3
VDD
—
Power supply terminal (+5V)
4
VSS
—
Ground terminal
5
AVSS1
—
Ground terminal (for A/D conversion)
6
VCOC
I
Control signal input for the internal VCO Not used (fixed at “L”)
7
AVDD1
—
Power supply terminal (+5V) (for A/D conversion)
8
VCOOUT
O
Signal output of the internal VCO Not used (open)
9
MCK1 (768FS)
I
Master clock signal (768Fs) input terminal Not used (fixed at “H”)
10
MCK2 (384FS)
I
Master clock signal (384Fs) input terminal
11
MCKOUT
O
Master clock signal output terminal Not used (open)
12
MCKSEL
I
Input terminal for clock signal setting internal VCO or MCK2 (pin !º)
Internal VCO used: “L”, MCK2 (pin !º) used: “H” (fixed at “H”)
Internal VCO used: “L”, MCK2 (pin !º) used: “H” (fixed at “H”)
13
MUTE
I
Mute signal input of the serial interface Not used (fixed at “H”)
14
DIN
I
Program data serial input from the master controller (IC301)
15
VSS
—
Ground terminal
16
SCK
I
Program data transfer clock signal input from the master controller (IC301)
17
CE
I
Program data load input from the master controller (IC301)
18
DOUT
O
Serial data output to the master controller (IC301)
19
BUSY
O
Busy signal at serial data transfer output to the master controller (IC301)
20
RESET
I
Reset signal input from the master controller (IC301) “L”: reset
21 to 27
TEST
I
Not used (fixed at “L”)
28
VDD
—
Power supply terminal (+5V)
29
VSS
—
Ground terminal
30 to 38
TEST
I
Not used (fixed at “L”)
39
M1
O
Parallel data (LSB) output terminal Not used (open)
40
VSS
—
Ground terminal
41
M2
O
42
M3
O
43
M4
O
44
M5
O
45
M6
O
46
M7
O
47
M8
O
48
M9
O
49
M10
O
50
M11
O
51
M12
O
52
M13
O
53
VDD
—
Power supply terminal (+5V)
54
VSS
—
Ground terminal
55
M14
O
Parallel data output terminal Not used (open)
56
M15
O
Parallel data output terminal Not used (open)
57
M16
O
Parallel data (MSB) output terminal Not used (open)
58 to 64
TEST
O
Not used (open)
65
VSS
—
Ground terminal
66 to 74
TEST
O
Not used (open)
Parallel data output terminal Not used (open)
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