Sony CDX-G1100U / CDX-G1100UE / CDX-G1101U / CDX-G1102U / CDX-G1150U / CDX-G1151U / CDX-G1152U / CDX-G1180UM Service Manual ▷ View online
CDX-G1100U/G1100UE/G1101U/G1102U/G1150U/G1151U/G1152U/G1180UM
25
Pin No.
Pin Name
I/O
Description
66, 67
DEBUG_6, DEBUG_7
O
Not used
68
BEEP
O
Beep sound drive signal output to the power amplifi er
69, 70
NC
O
Not used
71
RE_ON
O
Jog dial pulse pull-up signal output terminal
72, 73
RE-IN1, RE-IN0
I
Jog dial pulse input from the rotary encoder
74 to 77
NC
O
Not used
78, 79
KEYIN1, KEYIN0
I
Front panel key input terminal
80
RC_IN0
I
Rotary commander key input terminal
81
RC_IN1
I
Rotary commander shift key input terminal
82
MECHA_ON
I
Power detection signal input terminal for CD mechanism section
“H”: CD mechanism power on
“H”: CD mechanism power on
83, 84
NC
O
Not used
85
VSS4
-
Ground terminal
86
VDD4
-
Power supply terminal (+3.3V)
87 to 89
NC
O
Not used
90
NOSE_SW
I
Front panel remove/attach detection signal input terminal “L”: Front panel is attached
91, 92
NC
O
Not used
93
MEC_DSW
I
Chucking end detection switch input terminal
94
MEC_LSW
I
Limit in detection switch input terminal
95
FILT
I
Filter terminal for PLL
96
MEC_LOAD
O
Loading motor drive signal (loading direction) output terminal “H”: motor on
97
MEC_INSW
I
Disc insert detection switch input terminal
98
MEC_SELFSW
I
Self loading position detection switch input terminal
99
DRV_ON
O
Driver control signal output to the CD mechanism deck block
100
MEC_EJECT
O
Loading motor drive signal (eject direction) output terminal “H”: motor on
CDX-G1100U/G1100UE/G1101U/G1102U/G1150U/G1151U/G1152U/G1180UM
26
Pin No.
Pin Name
I/O
Description
1
LFOUT
O
Audio signal (front L-ch) output terminal
2
LROUT
O
Audio signal (rear L-ch) output terminal
3
LVRIN
I
Audio signal (L-ch) input terminal
4
DACOUT_L
O
Audio signal (L-ch) output terminal
5
DACOUT_R
O
Audio signal (R-ch) output terminal
6
RVRIN
I
Audio signal (R-ch) input terminal
7
RROUT
O
Audio signal (rear R-ch) output terminal
8
RFOUT
O
Audio signal (front R-ch) output terminal
9
L1_IN
I
Audio signal (tuner L-ch) input terminal
10
R1_IN
I
Audio signal (tuner R-ch) input terminal
11
L2_IN
I
Audio signal (L-ch) input terminal Not used
12
R2_IN
I
Audio signal (R-ch) input terminal Not used
13
L3_IN_P
I
Audio signal (AUX L-ch) input terminal (positive)
14
L3_IN_N
I
Audio signal (AUX L-ch) input terminal (negative)
15
R3_IN_P
I
Audio signal (AUX R-ch) input terminal (positive)
16
R3_IN_N
I
Audio signal (AUX R-ch) input terminal (negative)
17, 18
ATEST01 (OPN),
ATEST02 (OPN)
O
Analog test output terminal Not used
19
VREFOUT
O
Reference voltage output terminal Not used
20
VREF_ADC
O
External capacitor connection terminal for audio A/D converter reference voltage
21
AVSS2
-
Ground terminal (analog system)
22
AVDD2
-
Power supply terminal (+3.3V) (analog system)
23 to 26
NC
-
Not used
27
CD_DI
O
Serial data output to the digital servo processor
28
CD_CL
O
Serial data transfer clock signal output to the digital servo processor
29
CD_DO
I
Serial data input from the digital servo processor
30
CD_CE
O
Chip enable signal output to the digital servo processor
31
DVDD
-
Power supply terminal (+3.3V) (digital system)
32
DVSS
-
Ground terminal (digital system)
33 to 36
GP30 (NCO) to
GP33 (NCO)
I/O
Not used
37
SBSY
I
CD sub-code block sync signal input from the digital servo processor
38
SFSY
I
CD sub-code fl ame sync signal input from the digital servo processor
39
PW
I
CD sub-code PW data input from the digital servo processor
40
SBCK
I
CD sub-code data transfer clock signal input from the digital servo processor
41
DVDD
-
Power supply terminal (+3.3V) (digital system)
42
DVSS
-
Ground terminal (digital system)
43
REG1_EXTR (OPN)
O
Internal regulator reserve terminal Not used
44
DVDD15
O
External capacitor connection terminal for internal regulator
45
TXD1
O
UART data output to the system controller
46
RXD1
I
UART data input from the system controller
47
SMONI
O
Watch-dog timer status monitor output to the system controller
48
OPCDM
I
External decode permission signal input from the digital servo processor
49
DVDD
-
Power supply terminal (+3.3V) (digital system)
50
DVSS
-
Ground terminal (digital system)
51
RESETB
I
Reset signal input from the system controller “L”: reset
52
SIFCK
I
Serial data transfer clock signal input from the system controller
53
SIFDI
I
Serial data input from the system controller
54
SIFDO
O
Serial data output to the system controller
55
SIFCE
I
Chip enable signal input from the system controller
56
BUSYB
O
Busy signal output to the system controller “L”: busy
57
CD_BUSYB
I
Busy signal input from the digital servo processor “L”: busy
58
LRCK
I
L/R sampling clock signal input from the digital servo processor
59
BCK
I
Bit clock signal input from the digital servo processor
60
DATA
I
Audio data input from the digital servo processor
61
MCLK
I
Master clock signal input from the digital servo processor
62
USB_IN
O
USB device detection signal output to the system controller “L”: USB device is connected
63 to 65
GP45 (NCO) to
GP47 (NCO)
I/O
Not used
MAIN BOARD IC601 LC786800E-6C07-H (USB CONTROLLER, INPUT SELECTOR, AUDIO DSP, ELECTRICAL VOLUME)
CDX-G1100U/G1100UE/G1101U/G1102U/G1150U/G1151U/G1152U/G1180UM
27
Pin No.
Pin Name
I/O
Description
66
DVSS
-
Ground terminal (digital system)
67
DVDD
-
Power supply terminal (+3.3V) (digital system)
68
UDM1
I/O
Two-way USB data (–) bus with the USB connector
69
UDP1
I/O
Two-way USB data (+) bus with the USB connector
70
DVSS
-
Ground terminal (for digital system)
71
UDM2
I/O
Two-way USB data (–) bus terminal Not used
72
UDP2
I/O
Two-way USB data (+) bus terminal Not used
73
XVDD
-
Power supply terminal (+3.3V) (for oscillation circuit)
74
X12IN
I
System clock input terminal (12 MHz)
75
X12OUT
O
System clock output terminal (12 MHz)
76
XVSS
-
Ground terminal (for oscillation circuit)
77
AFILT
O
Charge pump output terminal for PLL
78, 79
VVDD2, VVDD3
-
Power supply terminal (+3.3V) (for PLL)
80
DVSS
-
Ground terminal (digital system)
81
DVDD
-
Power supply terminal (+3.3V) (digital system)
82
CP_SCL
O
Serial data transfer clock signal output to the EEPROM
83
CP_SDA
I/O
Two-way data bus with the EEPROM
84
CP_RESET
O
Reset signal output terminal Not used
85
CD_RESB
O
Reset signal output to the digital servo processor “L”: reset
86
CMD_ERR
O
Command error signal output to the system controller “H”: error
87
TEST0 (GND)
I
Test mode setting terminal Fixed at “L”
88
DVDD
-
Power supply terminal (+3.3V) (digital system)
89
DVSS
-
Ground terminal (for digital system)
90
DVDD15
O
External capacitor connection terminal for internal regulator
91
JTRSTB (IPD)
I
Reset signal input terminal (for JTAG) Normally: fi xed at “L”
92
JTCK (IPD)
I
Clock signal input terminal (for JTAG) Normally: fi xed at “L”
93
JTDI (IPD)
I
Data input terminal (for JTAG) Normally: fi xed at “L”
94
JTMS (IPU)
I
Mode selection signal input terminal (for JTAG) Normally: fi xed at “H”
95
JTDO (O)
O
Data output terminal (for JTAG) Normally: open
96
JTRTCK (O)
O
Return clock signal output terminal (for JTAG) Normally: open
97
TEST1 (GND)
I
Test mode setting terminal Fixed at “L”
98
AVDD1
-
Power supply terminal (+3.3V) (analog system)
99
AVSS1
-
Ground terminal (analog system)
100
LRREF
O
External capacitor connection terminal for audio D/A converter and electrical volume reference
voltage
voltage
CDX-G1100U/G1100UE/G1101U/G1102U/G1150U/G1151U/G1152U/G1180UM
28
MAIN BOARD IC701 LC78615E-01US-H (RF AMP, DIGITAL SERVO PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
EFMIN
I
RF signal input terminal
2
RFOUT
O
RF signal output terminal
3
LPF
-
External low-pass fi lter capacitor connection terminal for DC level detection of RF signal
4
PHLPF
-
External low-pass fi lter capacitor connection terminal for scratch detection
5
AIN
I
Main beam (B) input from the CD mechanism deck block
6
CIN
I
Main beam (C) input from the CD mechanism deck block
7
BIN
I
Main beam (A) input from the CD mechanism deck block
8
DIN
I
Main beam (C) input from the CD mechanism deck block
9
SLCISET
-
External resistor connection terminal for current setting of SLCO output
10
RFMON
-
Internal analog signal monitor terminal of LSI Not used
11
VREF
O
Reference voltage (+1.65V) output terminal for RF
12
JITTC
-
External capacitor connection terminal for jitter detection
13
EIN
I
Sub beam (F) input from the CD mechanism deck block
14
FIN
I
Sub beam (E) input from the CD mechanism deck block
15
TE
O
Tracking error signal output terminal
16
TEIN
I
Tracking error signal input terminal
17
AVSS
-
Ground terminal (analog system)
18
AVDD
-
Power supply terminal (+3.3V) (analog system)
19
LDD
O
Laser power control signal output to the CD mechanism deck block
20
LDS
I
Laser power detection signal input from the CD mechanism deck block
21
FDO
O
Focus coil control signal output to the CD mechanism deck block
22
TDO
O
Tracking coil control signal output to the CD mechanism deck block
23
SLDO
O
Sled motor control signal output to the CD mechanism deck block
24
SPDO
O
Spindle motor control signal output to the CD mechanism deck block
25
VVSS1
-
Ground terminal (for EFMPLL)
26, 27
PDOUT1, PDOUT0
O
Charge pump output terminal for EFMPLL
28
PCKIST
-
External resistor connection terminal for charge pump current setting for EFMPLL
29
VVDD1
-
Power supply terminal (+3.3V) (for EFMPLL)
30, 31
NC
-
Not used
32
DVDD15
-
External power capacitor connection terminal for digital system power
33
DVDD
-
Power supply terminal (+3.3V) (digital system)
34
DVSS
-
Ground terminal (digital system)
35
TEST
I
Test mode setting terminal Fixed at “L”
36
L_SW
I
Limit in detection switch input terminal
37, 38
NC
-
Not used
39
OPCDM
O
External decode permission signal output to the audio DSP
40
SBSY
O
CD sub-code block sync signal output to the audio DSP
41
SFSY
O
CD sub-code fl ame sync signal output to the audio DSP
42
PW
O
CD sub-code PW data output to the audio DSP
43
SBCK
O
CD sub-code data transfer clock signal output to the audio DSP
44
CE
I
Chip enable signal input from the audio DSP
45
CL
I
Serial data transfer clock signal input from the audio DSP
46
DI
I
Serial data input from the audio DSP
47
DO
O
Serial data output to the audio DSP
48
RESB
I
Reset signal input from the audio DSP “L”: reset
49
BUSYB
O
Busy signal output to the audio DSP “L”: busy
50
MCLK
O
Master clock signal output to the audio DSP
51
LRCK
O
L/R sampling clock signal output to the audio DSP
52
BCK
O
Bit clock signal output to the audio DSP
53
DATA
O
Audio data output to the audio DSP
54 to 56
SMOIN0 to SMOIN2
O
Servo internal signal monitor output terminal Not used
57
MODE
I
LSI operation mode setting terminal Fixed at “H”
58
DVDD15
-
External power capacitor connection terminal for digital system power
59
DVDD
-
Power supply terminal (+3.3V) (digital system)
60
XVSS
-
Ground terminal (for oscillation circuit)
61
XOUT
O
System clock output terminal (16.934 MHz)
62
XIN
I
System clock input terminal (16.934 MHz)
63
XVDD
-
Power supply terminal (+3.3V) (for oscillation circuit)
64
SLCO
O
Slice level control signal output terminal
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