Sony CDX-605 / XDC-40 (serv.man2) Service Manual ▷ View online
CDX-605
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– 30 –
7-7.
SCHEMATIC DIAGRAM – MAIN Section (2/2) –
•
See page 17 for Waveforms.
•
See page 31 for IC Block Diagrams.
CDX-605
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– 32 –
• IC Block Diagrams
IC11
CXA1992BR (RF BOARD)
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+
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+
1
2
3
4
5
6
7
8
9
10
20
19
17
16
15
14
13
12
11
21
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24
25
26
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29
30
31
32
33
34
35
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37
38
39
40
41
42
43
44
45
46
52
51
50
49
48
47
+
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+
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+
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+
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+
+
–
+
–
+
–
+
–
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+
+
–
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+
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+
+
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–
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+
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+
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+
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+
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+
+
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+
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+
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+
+
–
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18
–
+
–
+
–
+
+
–
+
–
–
+
Charge
up
FEO
FEI
FDFCT
FGD
FLB
FE_O
FE_M
SRCH
TGU
TG2
FSET
TA_M
TA_O
SL_P
SL_M
SL_O
ISET
VCC
VCC
LOCK
CLK
XLT
DATA
XRST
C. OUT
SENS1
SENS2
FOK
CC2
CC1
CB
CP
RF_I
RF_O
RF_M
RFTC
LD
PD
PD1
PD2
FE_BIAS
F
E
EI
VEE
TEO
LPFI
TEI
ATSC
TZC
VC
FZC
TM2
VEE
VEE
TM3
TM5
TM4
TM6
VCC
VCC
TM7
ISET
TTL
↓
IIL
IIL
↓
TTL
IIL
↓
TTL
IIL DATA REGISTER
INPUT SHIFT REGISTER
ADDRESS DECODER
SENS SELECTOR
OUTPUT DECODER
INPUT SHIFT REGISTER
ADDRESS DECODER
SENS SELECTOR
OUTPUT DECODER
DFCTO
IFB1-6
BAL1-4
TOG1-4
BAL1-4
TOG1-4
FS1-4
TG1-2
TM1-7
PS1-4
FOH
FOL
TGH
TGL
BALH
BALL
ATSC
TZC
FZC
FSET
TG2
VEE
VCC
FS1
FS2
FOCUS
PHASE COMPENSATION
PHASE COMPENSATION
DFCT
FS4
TRACKING
PHASE COMPENSATION
PHASE COMPENSATION
TG1
TM1
DFCT
FZC COMP.
VEE
VCC
VCC
TDFCT
TZC COMP.
ATSC
WINDOW
COMP.
WINDOW
COMP.
E-F BALANCE
WINDOW COMP.
WINDOW COMP.
TRK. GAIN
WINDOW COMP.
WINDOW COMP.
FO. BIAS
WINDOW
COMP.
WINDOW
COMP.
VEE
TGFL
TOG1
TOG2
TOG3
TOG4
BAL1
BAL2
BAL3
BAL4
IFB1
IFB2
IFB3
IFB4
IFB5
IFB6
FE AMP
VEE
E IV AMP
F IV AMP
VCC
APC
VCC
VEE
LASER POWER CONTROL
VEE
PD1 IV
AMP
AMP
PD2 IV
AMP
AMP
RF SUMMING
AMP
AMP
VCC
VEE
VEE
LEVEL S
LEVEL S
VEE
MIRR
VCC
DFCT
FOK
VCC
LDON
LPCL
LPC
TGFL
MIRR
DFCT1
CC1
IC52
BA6287F (RF BOARD)
IC301
BA6287F (MAIN BOARD)
1
2
3
4
OUT1
VM
VCC
FIN
8
7
6
5
GND
OUT2
VREF
RIN
CONTROL LOGIC
TSD
POWER
SAVE
DRIVER
DRIVER
IC101
CXD2530Q (MAIN BOARD)
1 2 3 4 5 6
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
43
42
42
41
40
40
39
38
38
37
36
35
34
33
32
31
31
50
49
49
48
47
47
46
45
44
88
89
89
90
91
91
92
93
93
94
95
96
97
98
99
100
81
82
82
83
84
84
85
86
87
71 70 69 68
67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
80 79 78 77 76 75 74 73 72
ASYMMETRY
CORRECTOR
DIGITAL
PLL
CLOCK
GENERATOR
D / A
INTERFACE
DIGITAL CLV
SUB CODE
PROCESSOR
TIMING
LOGIC
CPU
INTERFACE
SERVO
AUTO
SEQUENCER
ERROR
CORRECTOR
16K RAM
DIGITAL OUT
OSC
EFM
DEMODULATOR
TES6
VDD
VSS
EXCK
SBSO
SCOR
WFCK
TES5
EMPH
DOUT
C4M
FSTT
XTSL
MNT0
MNT1
MNT3
XROF
C2PO
RFCK
GFS
XPCK
XUGF
GTOP
VDD
VSS
TES4
BCK
TES3
PCMD
TES9
LRCK
WDCK
ASYE
ASYO
ASYI
ASYI
BIAS
RF
AVDD
CLTV
AVSS
FILI
FILO
PCO
PCO
VCTL
V16M
VCKI
VPCO1
VPCO2
TES1
TES0
LOCK
PWMI
MDP
MDS
VSS
MON
FOK
VDD
SPOD
XLON
SPOB
SPOC
CLKO
SPOA
DATO
XLTO
SEIN
CNIN
XLAT
CLOK
SENS
DATA
SQCK
SQSO
TES2
CKOUT
LMUT
RMUT
VDD
VSS
NC
XRST
VSS
NC
NC
VDD
NC
TES8
XVSS
VSS
XTAI
XTAO
VSS
XVDD
TES7
NC
VDD
NC
NC
VSS
– 33 –
IC102
SM5852FS-E2 (MAIN BOARD)
IC204
BA8272F-E2 (MAIN BOARD)
1
2
2
3
4
5
6
7
8
9
10
16
15
14
13
12
11
DIGITAL
SIGNAL
PROCESSOR
OUTPUT
INTERFACE
SYSTEM
CLOCK
INPUT
INTERFACE
SEQUENTIAL
CONTROL
MUTE
CONTROL
MODE
CONTROL
LRCI
BCKI
BCKI
DI
CLK
VSS
RSTN
TESTN
MUTEN
DB/DS
MOD2
MOD2
MOD1
OPT
VDD
LRCO
BCKO
DOUT
1
2
3
4
5
6
7
8
9
10
14
13
12
11
VCC
BUS ON
LINK OFF
CLK OUT
DATA OUT
DATA IN
BUS RESET
BUS DATA
VREF
BUS CLK
GND
BUS ON IN
BUS ON OUT
RESET
RESET
SWITCH
IC401
TC9464FN-EL (MAIN BOARD)
DIGITAL FILTER CIRCUIT
ATTENUATOR OPERATIONAL CIRCUIT
DEEMPHASIS FILTER CIRCUIT
D-
∆
MODULATION CIRCUIT
INTERFACE
CIRCUIT
TEST
CIRCUIT
OUTPUT
CIRCUIT
CIRCUIT
ANALOG
FILTER
TIMING
GENERATOR
OSC
MICROCOMPUTER
INTERFACE
CIRCUIT
OUTPUT
CIRCUIT
CIRCUIT
ANALOG
FILTER
1
2
3 4
5
6
7
8
9
10
20
19
18
17
16
15
14 13
12
11
21
22
23
24
LRCK
BCK
DATA
HS
(SM)
ATT
(EMP)
SH
(BS)
LA
VDX
XO
XI
GNDX
MCK
VDD
T1
P/S
VDA
RO
GNDA
VR
GNDA
LO
GNDD
ZD
VDA
– 34 –
7-8.
IC PIN FUNCTION DESCRIPTION
•
MAIN BOARD IC302 CXP84124-078Q (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Function
1
LIM.SW
I
Sled limit in detect switch (SW1) input terminal
“L”: When the optical pick-up is inner position
“L”: When the optical pick-up is inner position
2
BUSON
I
Bus on/off control signal input from the SONY bus interface (IC204) “H”: bus on
3
EJECT
I
Eject switch (SW303) input terminal “H” active
4
LOAD1
I
Save end detect switch (SW12) input terminal
“L”: When completion of the disc chucking operation
“L”: When completion of the disc chucking operation
5
LOAD2
I
Chucking end detect switch (SW11) input terminal
“L”: When completion of the disc chucking operation
“L”: When completion of the disc chucking operation
6
A.MUTE
O
Audio line muting on/off control signal output terminal “H”: muting on
7
EMPH
O
Emphasis mode output to the D/A converter (IC401) “L”: emphasis on
8
CH.R
O
Motor drive signal (save direction) output to the chucking motor drive (IC52)
“H” active *1
“H” active *1
9
CH.F
O
Motor drive signal (load chucking direction) output to the chucking motor drive (IC52)
“H” active *1
“H” active *1
10
—
O
Not used (open)
11
ELV.R
O
Motor drive signal (elevator down direction) output to the elevator motor drive (IC301)
“L” active *2
“L” active *2
12
ELV.ON
O
Mechanism deck section power supply on/off control signal output “H”: power on
13
CD RST
O
System reset signal output to the CXA1992AR (IC11), CXD2530Q (IC101) and SM5852FS
(IC102) “L”: reset
(IC102) “L”: reset
14
CDON
O
D/A converter and servo section power supply on/off control signal output “H”: power on
15 to 23
—
O
Not used (open)
24
AUTO ON/OFF
I
Setting terminal for the automatic adjustment “L”: automatic adjustment, “H”: manual
adjustement (solder across the BP302 terminal) Normally: fixed at “L”
adjustement (solder across the BP302 terminal) Normally: fixed at “L”
25 to 29
—
O
Not used (open)
30
RESET
I
System reset signal input from the reset signal generator (IC202) and SONY bus interface
(IC204) “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
(IC204) “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
31
EXTAL
I
Main system clock input terminal (8 MHz)
32
XTAL
O
Main system clock output terminal (8 MHz)
33
VSS
—
Ground terminal
34
TX
O
Sub system clock output terminal Not used (open)
35
TEX
I
Sub system clock input terminal Not used (fixed at “L”)
36
AVSS
—
Ground terminal (for A/D converter)
37
AVREF
I
Reference voltage (+5V) input terminal (for A/D converter)
38
ATRIBT
I
Selection input of the custom file, D-BASS, etc.
39
MCK
I
Input of signal for the fine adjustment (linear position sensor adjustment; RV301) of elevator
position (A/D input)
position (A/D input)
40
EHS
I
Elevator height position detect input from the RV302 (elevator height sensor) (A/D input)
41
H.TEMP
I
High temperature sensor input terminal Not used (open)
42
—
O
Not used (open)
43
MODE1
O
D-BASS control signal output to the SM5852FS (IC102)
44
MODE2
O
D-BASS control signal output to the SM5852FS (IC102)
45
MODE3
O
D-BASS control signal output Not used (open)
46, 47
—
O
Not used (open)
48
SCK
I
Serial data transfer clock signal input from the SONY bus interface (IC204)
49
SI
I
Serial data input from the SONY bus interface (IC204)
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