Sony STR-DA5000ES Service Manual ▷ View online
97
STR-DA5000ES
Pin No.
Pin Name
I/O
Description
117
VSS
—
Ground terminal
118, 119
GP5, GP4
—
Not used
120
GP3
O
Error signal output to the main system controller
121
NC
—
Not used
122
A0
O
Address signal output to the S-RAM
123 to 125
D4 to D2
I/O
Two-way data bus with the S-RAM
126
VDDE
—
Power supply terminal (+3.3V)
127
VSS
—
Ground terminal
128, 129
D1, D0
I/O
Two-way data bus with the S-RAM
130 to 132
GP2 to GP0
—
Not used
133
SDCLK
O
SD-RAM clock signal output terminal Not used
134
CLKEN
I
Fixed at “H” in this set
135
DQM
O
Output terminal of data input/output mask Not used
136
EXLOCK
I
Lock signal input from the main system controller
137
VDDI
—
Power supply terminal (+2.5V)
138
VSS
—
Ground terminal
139
MCLK2
O
System clock output terminal (13.5 MHz)
140
PM
I
PLL initialize signal input from the main system controller
141
BST
I
Boot strap signal input from the main system controller
142
BOOT
I
Boot mode control signal input terminal Not used
143
TST
I
Not used
144
MCLK1
I
System clock input terminal (13.5 MHz)
98
STR-DA5000ES
•
DIGITAL BOARD IC2401, IC2426 ISPLSI2032VE-110LTN44-MOD (GPR)
Pin No.
Pin Name
I/O
Description
1
EDGE
I
Clock signal input terminal
2
BCKIN
I
Bit clock signal input terminal
3
BCK2IN
I
Not used (open)
4
I/O
I/O
Not used (open)
5
MCK
I
Serial data transfer clock signal input terminal
6
VCC
—
Power supply terminal (+3.3V)
7
BSCAM
—
Not used (open)
8
IN Q/TDI
I
Not used (open)
9, 10
I/O
I/O
Not used (open)
11
BCKAOUT
O
IC2401: Bit clock signal output, IC2426: Not used (open)
12
MCKOUT
O
Serial data transfer clock signal output terminal
13
DIOUT_8
O
IC2401: SBR-ch analog audio signal output, IC2426: Not used (open)
14
DIOUT_7
O
IC2401: SBL-ch analog audio signal output, IC2426: Not used (open)
15
DIOUT_6
O
IC2401: SR-ch analog audio signal output, IC2426: Not used (open)
16
DIOUT_5
O
IC2401: SL-ch analog audio signal output, IC2426: Not used (open)
17
GND
—
Ground terminal
18
IN 1/TDO
O
Not used (open)
19
DIOUT_4
O
W-ch analog audio signal output terminal
20
DIOUT_3
O
C-ch analog audio signal output terminal
21
DIOUT_2
O
R-ch analog audio signal output terminal
22
DIOUT_1
O
L-ch analog audio signal output terminal
23 to 26
I/O
I/O
Not used (open)
27
Y2/TCK
—
Not used (open)
28
VCC
—
Power supply terminal (+3.3V)
29
Y1/RESET
I
Reset signal input terminal
30
TMS
—
Not used (open)
31
DATAEN
I
Not used (connected to VCC)
32
CLKSEL
I
Not used (connected to VCC)
33
FS
I
IC2401: Not used (connected to ground), IC2426: Clock signal input
34
I/O
I/O
Not used (open)
35
DATA_1
I
IC2401: L-ch analog audio signal input, IC2426: analog audio signal input
36
DATA_2
I
IC2401:R-ch analog audio signal input, IC2426: analog audio signal input
37
DATA_3
I
IC2401: SL-ch analog audio signal input, IC2426: analog audio signal input
38
DATA_4
I
IC2401: SR-ch analog audio signal input, IC2426: analog audio signal input
39
GND
—
Ground terminal
40
GOE0
—
Not used (open)
41
DATA_5
I
IC2401: C-ch analog audio signal input, IC2426: Not used (open)
42
DATA_6
I
IC2401: W-ch analog audio signal input, IC2426: Not used (open)
43
DATA_7
I
IC2401: SBL-ch analog audio signal input, IC2426: Not used (open)
44
DATA_8
I
IC2401: SBR-ch analog audio signal inputl, IC2426: Not used (connected to ground)
99
STR-DA5000ES
•
DIGITAL BOARD IC2301 CXD9722TQ (LIP SYNC ADJUST)
Pin No.
Pin Name
I/O
Description
1 to 5
D1 to D5
I/O
Serial data input/output terminal with the DRAM
6
VDD
—
Power supply terminal (+3.3V)
7, 8
D6, D7
I/O
Serial data input/output terminal with the DRAM
9
VSS
—
Ground terminal
10
WE
O
Write enable signal output to the DRAM
11
CAS
O
Column address strobe signal output to the DRAM
12
RAS
O
Row address strobe signal output to the DRAM
13
CS
O
Chip select signal output to the DRAM
14
CLK
O
Serial data transfer clock signal output to the DRAM
15
CEK
O
Chip enable signal output to the DRAM
16
VDD
—
Power supply terminal (+3.3V)
17, 18
A11, A10
O
Address signal output to the DRAM
19 to 22
A0 to A3
O
Address signal output to the DRAM
23
VSS
—
Ground terminal
24 to 29
A9 to A4
O
Address signal output to the DRAM
30
VSS
—
Ground terminal
31
DRSO
O
SR-ch analog audio signal output terminal
32
DLSO
O
SL-ch analog audio signal output terminal
33
DEXRO
O
Not used (open)
34
DLFEO
O
W-ch analog audio signal output terminal
35
DCO
O
C-ch analog audio signal output terminal
36
VDD
O
Power supply terminal (+3.3V)
37
DRO
O
R-ch analog audio signal output terminal
38
DLO
O
L-ch analog audio signal output terminal
39
VSS
—
Ground terminal
40
DMRO
O
SBR-ch analog audio signal output terminal
41
DMLO
O
SBL-ch analog audio signal output terminal
42
VSS
—
Ground terminal
43
VDD
—
Power supply terminal (+3.3V)
44
DLDRO
O
Audio serial data output terminal
45
CSWO
O
Audio serial data output terminal
46
SLSRO
O
Audio serial data output terminal
47
FLFRO
O
Audio serial data output terminal
48
VSS
—
Ground terminal
49
SPDIFO
O
SPDIF signal output terminal Not used
50
TEST1
I
Test mode setting terminal Not used
51
TRST
I
Reset signal input terminal for test Not used
52
TMS
I
Mode setting terminal for test Not used
53
TCK
I
Clock signal input terminal for test Not used
54
TDI
I
Serial data input terminal for test Not used
55
TDO
O
Serial data output terminal for test Not used
56
TEST2
I
Test mode setting terminal Not used
57
SPDIFI
I
SPDIF signal input terminal Not used
58
VSS
—
Ground terminal
59
LRCKI
I
L/R sampling clock signal (44.1 kHz) input from the digital signal processor
100
STR-DA5000ES
Pin No.
Pin Name
I/O
Description
60
BCKI
I
Bit clock signal (2.8224 MHz) input from the digital signal processor
61
VDD
—
Power supply terminal (+3.3V)
62
VSS
—
Ground terminal
63
DLDRI
I
Audio serial data input from the digital signal processor
64
CSWI
I
Audio serial data input from the digital signal processor
65
SLSRI
I
Audio serial data input from the digital signal processor
66
FLFRI
I
Audio serial data input from the digital signal processor
67
TEST3
I
Test mode setting terminal Not used
68
CLK512
I
Serial data transfer clock signal input terminal
69
VSS
—
Ground terminal
70
XRST
I
Reset signal input from the main system controller
71
VDD
—
Power supply terminal (+3.3V)
72
SCLK
I
Serial data transfer clock signal input from the main system controller
73
XCS
I
Chip select signal input from the main system controller
74
SI
I
Serial data input from the main system controller
75
SO
O
Serial data output to the main system controller
76
DEXRI
I
Not used (connected to ground)
77
DMLI
I
SBL-ch analog audio signal input terminal
78
DMRI
I
SBR-ch analog audio signal input terminal
79
VSS
—
Ground terminal
80
PHRI
I
Clock signal input terminal
81
BCKAI
I
Bit clock signal input from the GPR
82
DQM
O
Not used
83
DLI
I
L-ch analog audio signal input terminal
84
DRI
I
R-ch analog audio signal input terminal
85
DCI
I
C-ch analog audio signal input terminal
86
DLFEI
I
W-ch analog audio signal input terminal
87
DLSI
I
SL-ch analog audio signal input terminal
88
DRSI
I
SR-ch analog audio signal input terminal
89
VSS
—
Ground terminal
90 to 95
D15 to D10
I/O
Serial data input/output terminal with the DRAM
96
VDD
—
Power supply terminal (+3.3V)
97, 98
D9, D8
I/O
Serial data input/output terminal with the DRAM
99
VSS
—
Ground terminal
100
D0
I/O
Serial data input/output terminal with the DRAM
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