Sony STR-DA5000ES Service Manual ▷ View online
89
STR-DA5000ES
– REG Board –
IC931
DSD1751DBQR
DSDL
DBCK
1
20
DSDR
DSCK
2
19
PBCK
PSCK
3
18
PDATA
MS
4
17
PLRCK
MC
5
16
DGND
MD
6
15
VDD
ZEROR/ZEROA
7
14
VCC
ZEROL/NA
8
13
VOUTL
VCOM
9
12
VOUTR
AGND
10
11
MUX
DSD
FILTER
PCM
I/F
PCM
FILTER
(X8 DF)
MULTI-LEVEL
DELTA-SIGMA
MODULATOR
MULTI-LEVEL
DAC
ANALOG
LPF
DSD
I/F
MUX
MODE
CONTROL
IC940, 941
TC74VHC541FT (EL)
8
15
16
10
14
13
12
11
9
6
7
4
2
3
1
VCC
G2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
GND
A8
A7
A6
A5
A4
A3
A2
A0
A1
20 19
18
17
5
IC2801
DSD1608PAHR
DAC
DSD3
VCOM2
40
26
DSD4
VCC7
41
25
DSD5
VCC6
42
24
DSD6
AGND5
43
23
DSD7
VCC5
44
22
DSD8
AGND4
45
21
PDATA1
VCC4
46
20
PDATA2
AGND3
47
19
PDATA3
VCC3
48
18
PDATA4
AGND2
49
17
PBCK
VCC2
50
16
PLRCK
VCC1
51
15
VDD1
VCOM1
52
14
DGND1
DSD2
1
39
MDI
DSD1
2
38
MS
DBCK
3
37
MC
RST
4
36
MDO
VDD2
5
35
ZERO1
DSCK
6
34
ZERO2
PSCK
7
33
ZERO38
DGND2
8
32
VOUT4
VOUT5
9
31
VOUT3
VOUT6
10
30
VOUT2
VOUT7
11
29
VOUT1
VOUT8
12
28
AGND1
AGND6
13
27
FUNCTION
CONTROL
PCM
I/F
SYSTEM
CLOCK
SYSTEM
CLOCK
ZERO
DETECT
DSD
I/F
DSD
FILTER
ENHANCED
MULTILEVEL
DELTA-SIGMA
MODULATOR
DAC
OUTPUT AMP
AND
LOW-PASS
FILTER
OUTPUT AMP
AND
LOW-PASS
FILTER
DAC
OUTPUT AMP
AND
LOW-PASS
FILTER
DAC
OUTPUT AMP
AND
LOW-PASS
FILTER
PCM
FILTER
(X8 DF)
DAC
DAC
OUTPUT AMP
AND
LOW-PASS
FILTER
OUTPUT AMP
AND
LOW-PASS
FILTER
DAC
OUTPUT AMP
AND
LOW-PASS
FILTER
DAC
OUTPUT AMP
AND
LOW-PASS
FILTER
90
STR-DA5000ES
6-59.
IC PIN FUNCTION DESCRIPTION
•
DIGITAL BOARD IC2121 LC89056W-E (DIGITAL AUDIO INTERFACE RECEIVER)
Pin No.
Pin Name
I/O
Description
1
DISEL
I
Selection signal input terminal of data input terminal Fixed at “L” in this set
2
DOUT
O
Digital data output to the external output terminal Not used
3
DIN0
I
Digital data input from the external input terminal
4, 5
DIN1,DIN2
I
Digital data input from the external input terminal Fixed at “L” in this set
6
D. GND
—
Ground terminal (for digital)
7
DVDD
—
Power supply terminal (+3.3V) (for digital)
8
R
I
Input terminal for VCO gain control
9
VIN
I
Input terminal for VCO free-run frequency setting
10
LPF
O
PLL loop filter setting terminal
11
AVDD
—
Power supply terminal (+3.3V) (for analog)
12
AGND
—
Ground terminal (for analog)
13
CKOUT
O
Audio clock signal output to the selector
14
BCK
O
Bit clock signal (2.8224 MHz) output to the digital signal processor and A/D converter
15
LRCK
O
L/R sampling clock signal (44.1 kHz) output to the digital signal processor and A/D converter
16
DATAO
O
Audio serial data output to the digital signal processor and main system controller
17
XSTATE
O
Source clock selection monitor output to the main system controller
18
DGND
—
Ground terminal (for digital)
19
DVDD
—
Power supply terminal (+3.3V) (for digital)
20
XMCK
O
System clock signal (12.288 MHz) output to the A/D converter
21
XOUT
O
System clock output terminal (12.288 MHz) Not used
22
XIN
I
System clock input terminal (12.288 MHz)
23
EMPHA
O
Channel status emphasis information output terminal Not used
24
AUDIO
O
Channel status bit 1 output to the digital signal processor
25
CSFLAG
O
Channel status head 40 bit renewal flag output terminal Not used
26 to 29
F0/P0/C0 to
F3/P3/C3
O
Output terminal of input frequency calculation result Not used
30
DVDD
—
Power supply terminal (+3.3V) (for digital)
31
DGND
—
Ground terminal (for digital)
32
AUTO
O
Not used
33
BPSYNC
O
Non-PCM burst preamble sync signal output terminal Not used
34
ERROR
O
PLL lock error signal and data error flag output to the digital signal processor and main system
controller
controller
35
DO
O
Read data output to the main system controller
36
DI
I
Write data input from the main system controller
37
CE
I
Chip enable signal input from the main system controller
38
CLK
I
Clock signal input from the main system controller
39
XSEL
I
Selection signal input terminal of crystal oscillator frequency Fixed at “H” in this set
40, 41
MODE0, MODE1
I
Mode setting terminal Fixed at “L” in this set
42
DGND
—
Ground terminal (for digital)
43
DVDD
—
Power supply terminal (+3.3V) (for digital)
44, 45
DOSEL0, DOSEL1
I
Output data format selection signal input terminal Fixed at “L” in this set
46
CKSEL0
I
Output clock selection signal input terminal Fixed at “L” in this set
47
CKSEL1
I
Output clock selection signal input from the main system controller
48
XMODE
I
System reset signal input from the main system controller “L”: reset
91
STR-DA5000ES
Pin No.
Pin Name
I/O
Description
50
RY
O
Relay drive signal output terminal
51
SHIFT
O
Serial data transfer clock signal output to the PCM/PWM processor
52
/SO1 SCDT
O
Serial data output to the PCM/PWM processor
53
/SI1 SR-B
O
Relay drive signal output terminal Not used
54
C RY
O
Not used (open)
55
SB RY
O
Not used (open)
56
VCC
—
Power supply terminal (+3.3V)
57
SP RY
O
Relay drive signal output terminal Not used (open)
58
HP RY
O
Relay drive signal output terminal (for headphone)
59
—
I
Not used (open)
60
U-SUB2
O
Serial data signal output to main system controller
61
—
I
Not used (open)
62
FORMAT
I
Not used (connected to VDD)
63
HENCYO
I
Not used (connected to VDD)
64
MUTE
I
Muting on/off control signal output terminal Not used (open)
92
STR-DA5000ES
•
DIGITAL BOARD IC2201 CXD9718Q (DIGITAL SIGNAL PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
VSS
—
Ground terminal
2
XRST
I
System reset signal input from the main system controller “L”: reset
3
EXTIN
I
Master clock signal input terminal Not used
4
FS2
I
Sampling frequency selection signal input terminal Not used
5
VDDI
—
Power supply terminal (+2.5V)
6
FS1
I
Sampling frequency selection signal input terminal Not used
7
PLOCK
O
Internal PLL lock signal output terminal Not used
8
VSS
—
Ground terminal
9
MCLK1
I
System clock input terminal (13.5 MHz)
10
VDDI
—
Power supply terminal (+2.5V)
11
VSS
—
Ground terminal
12
MCLK2
O
System clock output terminal (13.5 MHz)
13
MS
I
Master/slave setting terminal “L”: internal clock, “H”: external clock
Fixed at “L” in this set
Fixed at “L” in this set
14
SCKOUT
O
Internal system clock output terminal Not used
15
LRCKI1
I
L/R sampling clock signal (44.1 kHz) input from the A/D converter and digital audio interface
receiver
receiver
16
VDDE
—
Power supply terminal (+3.3V)
17
BCKI1
I
Bit clock signal (2.8224 MHz) input from the A/D converter and digital audio interface receiver
18
SDI1
I
Audio serial data input from the A/D converter
19
LRCKO
O
L/R sampling clock signal (44.1 kHz) output to the digital signal processor
20
BCKO
O
Bit clock signal (2.8224 MHz) output to the digital signal processor
21
VSS
—
Ground terminal
22
KFSIO
I
Audio clock signal input from the digital audio interface receiver
23 to 26
SDO1 to SDO4
O
Audio serial data output to the digital signal processor
27
SPDIF
O
SPDIF signal output terminal Not used
28
LRCKI2
I
L/R sampling clock signal (44.1 kHz) input from the A/D converter and digital audio interface
receiver
receiver
29
BCKI2
I
Bit clock signal (2.8224 MHz) input from the A/D converter and digital audio interface receiver
30
SDI2
I
Audio serial data input from the digital audio interface receiver
31
VSS
—
Ground terminal
32
HACN
O
Acknowledge signal output to the main system controller
33
HDIN
I
Serial data input from the main system controller
34
HCLK
I
Serial data transfer clock signal input from the main system controller
35
HDOUT
O
Serial data output to the main system controller
36
HCS
I
Chip select input from the main system controller
37
SDCLK
I
Write signal input from the system controller Not used
38
CLKEN
O
SD-RAM chip enable output terminal Not used
39
RAS
O
Row address strobe signal output terminal Not used
40
VDDI
—
Power supply terminal (+2.5V)
41
VSS
—
Ground terminal
42
CAS
O
Column address strobe signal output terminal Not used
43
DQM/OE0
O
Output terminal of data input/output mask Not used
44
CS0
O
Chip select signal output to the S-RAM
45
WE0
O
Write enable signal output to the S-RAM
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