Sony STR-DA5000ES Service Manual ▷ View online
93
STR-DA5000ES
Pin No.
Pin Name
I/O
Description
46
VDDE
—
Power supply terminal (+3.3V)
47
WMD1
I
External memory wait mode setting terminal Fixed at “H” in this set
48
VSS
—
Ground terminal
49
WMD0
I
External memory wait mode setting terminal Fixed at “H” in this set
50
PAGE2
O
External memory page selection signal output terminal Not used
51
VSS
—
Ground terminal
52, 53
PAGE1, PAGE0
O
External memory page selection signal output terminal Not used
54
BOOT
I
Boot mode control signal input terminal Not used
55
BTACT
O
Boot mode state display signal output terminal Not used
56
BST
I
Boot strap signal input from the main system controller
57
MOD1
I
Operation mode setting terminal “L”: enhanced mode, “H”: normal mode
Fixed at “H” in this set
Fixed at “H” in this set
58
MOD0
I
Operation mode setting terminal “L”: single chip mode, “H”: can not use
Fixed at “L” in this set
Fixed at “L” in this set
59
EXLOCK
I
PLL lock error signal and data error flag input from the digital audio interface receiver
60
VDDI
—
Power supply terminal (+2.5V)
61
VSS
—
Ground terminal
62, 63
A17, A16
O
Address signal output terminal Not used
64 to 66
A15 to A13
O
Address signal output to the S-RAM
67
GP10
I
L/R sampling clock signal (44.1 kHz) input terminal Not used
68
GP9
O
Read ready signal output to the main system controller
69
GP8
I
Channel status bit 1 input from the digital audio interface receiver
70
VDDI
—
Power supply terminal (+2.5V)
71
VSS
—
Ground terminal
72 to 75
D15 to D12
I/O
Two-way data bus with the S-RAM
76
VDDE
—
Power supply terminal (+3.3V)
77 to 80
D11 to D8
I/O
Two-way data bus with the S-RAM
81
VSS
—
Ground terminal
82 to 85
A9, A12 to A10
O
Address signal output to the S-RAM
86
TDO
O
Simplicity emulation data output terminal Not used
87
TMS
I
Simplicity emulation data input start and end terminal Not used
88
XTRST
I
Simplicity emulation non-sync break signal input terminal Not used
89
TCK
I
Simplicity emulation clock signal input terminal Not used
90
TDI
I
Simplicity emulation data input terminal Not used
91
VSS
—
Ground terminal
92 to 97
A8 to A3
O
Address signal output to the S-RAM
98, 99
D7, D6
I/O
Two-way data bus with the S-RAM
100
VDDI
—
Power supply terminal (+2.5V)
101
VSS
—
Ground terminal
102 to 105
D5 to D2
I/O
Two-way data bus with the S-RAM
106
VDDE
—
Power supply terminal (+3.3V)
107, 108
D1, D0
I/O
Two-way data bus with the S-RAM
109, 110
A2, A1
O
Address signal output to the S-RAM
111
VSS
—
Ground terminal
112
A0
O
Address signal output to the S-RAM
113
PM
I
PLL initialize signal input from the main system controller
94
STR-DA5000ES
Pin No.
Pin Name
I/O
Description
114, 115
SDI3, SDI4
I
Audio serial data input terminal Not used
116
SYNC
I
Sync/non-sync setting terminal “L”: sync, “H”: non-sync Fixed at “H” in this set
117 to 119
VSS
—
Ground terminal
120
VDDI
—
Power supply terminal (+2.5V)
95
STR-DA5000ES
•
DIGITAL BOARD IC2251 CXD9616BR (DIGITAL SIGNAL PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
VDDI
—
Power supply terminal (+2.5V)
2
EXTIN
I
Master clock signal input terminal Not used
3, 4
WMD1, WMD0
I
External memory wait mode setting terminal Fixed at “H” in this set
5
MOD1
I
Operation mode setting terminal “L”: enhanced mode, “H”: normal mode
Fixed at “H” in this set
Fixed at “H” in this set
6
MOD0
I
Operation mode setting terminal “L”: single chip mode, “H”: can not use
Fixed at “L” in this set
Fixed at “L” in this set
7
VSS
—
Ground terminal
8
XRST
I
System reset signal input from the main system controller “L”: reset
9
VSS
—
Ground terminal
10
SCKOUT
O
Internal serial clock signal output terminal Not used
11
VDDI (PLL)
—
Power supply terminal (+2.5V) (for PLL)
12
SYNC
I
Sync/non-sync setting terminal “L”: sync, “H”: non-sync Fixed at “H” in this set
13 to 15
PAGE2 to PAGE0
O
External memory page selection signal output terminal Not used
16
PLOCK
O
Internal PLL lock signal output terminal Not used
17
BTACK
I
Boot mode state display signal output terminal Not used
18
VDDE
—
Power supply terminal (+3.3V)
19
VSS
—
Ground terminal
20 to 22
D31 to D29
I/O
Two-way data bus with the S-RAM
23
A17
O
Address signal output terminal Not used
24
VSS
—
Ground terminal
25
SDO3
O
Audio serial data output to the lip sync adjust
26
SDO4
O
Audio serial data output to the lip sync adjust
27, 28
SDI1, SDI2
I
Audio serial data input from the digital signal processor
29
LRCKI1
I
L/R sampling clock signal (44.1 kHz) input from the digital signal processor
30
VSS
—
Ground terminal
31, 32
D28, D27
I/O
Two-way data bus with the S-RAM
33
A16
O
Address signal output terminal Not used
34
A15
O
Address signal output to the S-RAM
35
SDI3
I
Audio serial date input from the digital signal processor
36
L2
—
Not used
37
VDDI
—
Power supply terminal (+2.5V)
38
BCKI1
I
Bit clock signal (2.8224 MHz) input from the digital signal processor
39
SDI4
I
Audio serial data input from the digital signal processor
40
MS
I
Master/slave setting terminal “L”: internal clock, “H”: external clock
Fixed at “L” in this set
Fixed at “L” in this set
41, 42
A14, A13
O
Address signal output to the S-RAM
43, 44
D26, D25
I/O
Two-way data bus with the S-RAM
45
VSS
—
Ground terminal
46
BCKI2
I
Bit clock signal (2.8224 MHz) input terminal Not used
47, 48
FS2, FS1
I
Sampling frequency selection signal input terminal Not used
49
SPDIF
I
SPDIF signal input terminal Not used
50
A12
O
Address signal output to the S-RAM
51 to 53
D24 to D22
I/O
Two-way data bus with the S-RAM
54
VDDE
—
Power supply terminal (+3.3V)
96
STR-DA5000ES
Pin No.
Pin Name
I/O
Description
55
VSS
—
Ground terminal
56 to 58
D21 to D19
I/O
Two-way data bus with the S-RAM
59
A11
O
Address signal output to the S-RAM
60, 61
SDO1, SDO2
O
Audio serial data output to the lip sync adjust
62
KFSIO
I
Audio clock signal input from the digital audio interface receiver
63
LRCKO
O
L/R sampling clock signal (44.1 kHz) output terminal
64
BCKO
O
Bit clock signal (2.8224 MHz) output terminal
65
VDDI
—
Power supply terminal (+2.5V)
66
VSS
—
Ground terminal
67, 68
D18, D17
I/O
Two-way data bus with the S-RAM
69, 70
A10, A9
O
Address signal output to the S-RAM
71
CAS
O
Column address strobe signal output terminal Not used
72
RAS
O
Row address strobe signal output terminal Not used
73
VDDI
—
Power supply terminal (+2.5V)
74
HDIN
I
Serial data input from the main system controller
75
HCLK
I
Serial data transfer clock signal input from the main system controller
76
HCS
I
Chip select signal input from the main system controller
77, 78
A8, A7
O
Address signal output to the S-RAM
79, 80
D16, D15
I/O
Two-way data bus with the S-RAM
81
VSS
—
Ground terminal
82
HDOUT
O
Serial data output to the main system controller
83
HACN
O
Acknowledge signal output to the main system controller
84
CSO
O
Chip select signal output to the S-RAM
85
WEO
O
Write enable signal output to the S-RAM
86
A6
O
Address signal output to the S-RAM
87 to 89
D14 to D12
I/O
Two-way data bus with the S-RAM
90
VDDE
—
Power supply terminal (+3.3V)
91
VSS
—
Ground terminal
92 to 94
D11 to D9
I/O
Two-way data bus with the S-RAM
95
A5
O
Address signal output to the S-RAM
96
VDDI
—
Power supply terminal (+2.5V)
97
TCK
I
Simplicity emulation clock signal input terminal Not used
98
TDI
I
Simplicity emulation data input terminal Not used
99
TDO
O
Simplicity emulation data input terminal Not used
100
TMS
I
Simplicity emulation data input start and end select Not used
101
XTRST
I
Simplicity emulation non-sync break signal input terminal Not used
102
VSS
—
Ground terminal
103, 104
D8, D7
I/O
Two-way data bus with the S-RAM
105, 106
A4, A3
O
Address signal output to the S-RAM
107, 108
GP10, GP9
—
Not used
109
VDDI
—
Power supply terminal (+2.5V)
110
GP8
—
Not used
111
GP7
I
L/R sampling clock signal (44.1 kHz) input terminal
112
GP6
—
Not used
113, 114
A2, A1
O
Address signal output to the S-RAM
115, 116
D6, D5
I/O
Two-way data bus with the S-RAM
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