Sony STR-DA5000ES Service Manual ▷ View online
101
STR-DA5000ES
•
DIGITAL BOARD IC2601 MB91F155-3ES-X100 (MAIN SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
DSP CLK
O
Serial data transfer clock signal output to the digital signal processor
2
DSP HDIN
O
Serial data output to the digital signal processor
3
1BST SEL
O
Boot strap signal output to the clock select
4
1XRST
O
System reset signal output to the digital signal processor “L”: reset
5
1PM
O
PLL initialize signal output to the digital signal processor
6
1GP9
I
Read ready signal input from the digital signal processor
7
1BST
O
Boot strap signal output to the digital signal processor
8
1HCS
O
Chip select signal output to the digital signal processor
9
VSS
—
Ground terminal
10
1HDOUT
I
Serial data input from the digital signal processor
11
1HACN
I
Acknowledge signal input from the digital signal processor
12
2XRST
O
System reset signal output to the digital signal processor “L”: reset
13
2PM
O
PLL initialize signal output to the digital signal processor
14
2GP3
I
Read ready signal input from the digital signal processor
15
2BST
O
Boot strap signal output to the digital signal processor
16
2HCS
O
Chip select signal output to the digital signal processor
17
2HDOUT
I
Serial data input from the digital signal processor
18
2HACN
I
Acknowledge signal input from the digital signal processor
19
2EXLOCK
O
PLL lock error signal and data error flag output to the digital sigal processor
20
DIR-XMODE
O
System reset signal output to the digital audio interface receiver “L”: reset
21
DIR-CKSEL
O
Output clock selection signal output to the digital audio interface receiver
22
DIR-CLK
O
Clock signal output to the digital audio interface receiver
23
DIR-CE
O
Chip enable signal output to the digital audio interface receiver
24
DIR-DO
I
Read data input from the digital audio interface receiver
25
DIR-DI
O
Write data output to the digital audio interface receiver
26
VSS
—
Ground terminal
27
VCC
—
Power supply terminal (+3.3V)
28
DIR-ERROR
I
PLL lock error signal and data error flag input from the digital audio interface receiver
29
DIR-DATAO
I
Audio serial data input from the digital audio interface receiver
30
DIR-XSTATE
I
Source clock selection monitor input from the digital audio interface receiver
31
TA_XCS
O
Chip select signal output to the lip sync adjust
32
TA_SO
I
Serial data input from the lip sync adjust
33
TA_XRST
O
Reset signal output to the lip sync adjust
34
ADINT1
O
Reset signal output to the A/D converter
35
ADINT2
O
Reset signal output to the sub-2 system controller
36
D595OE
O
Output enable signal output to the TC74HC595AF
37
LAT1
O
Serial data latch pulse output to the TC74HC595AF
38
LAT2
O
Serial data latch pulse output to the TC74HC595AF
39
COM1CLK
O
Common clock signal output terminal
40
COM1DATA
O
Common data output terminal
41
COM2DATA
O
Common data output terminal
42
COM2CLK
O
Common data transfer clock signal output terminal
43
V595OE
O
Output enable signal output to the TC74HC595AF
44
VSS
—
Ground terminal
45
V595LAT
O
Serial data latch pulse output to the TC74HC595A
102
STR-DA5000ES
Pin No.
Pin Name
I/O
Description
46
FUNCLAT
O
Serial data latch pulse output to the TC74HCT7007AF
47
D.MIXLAT
O
Serial data latch pulse output to the TC74HCT7007AF
48
VDLLAT
O
Serial data latch pulse output to the TC74HCT7007AF
49
UPCONLAT
O
Serial data latch pulse output terminal Not used
50
MBUS-STS0
I
M-BUS status input from the sub system controller
51
A1OUT
O
Sircs signal output for the CTRL A1 II
52
MD2
I
Setting terminal for the CPU operational mode
53
MD1
I
Setting terminal for the CPU operational mode
54
MD0
I
Setting terminal for the CPU operational mode
55
RSTX
I
External reset signal input terminal
56
VCC
—
Power supply terminal (+3.3V)
57
X1
I
Main system clock input terminal (16.5 MHz)
58
X0
O
Main system clock output terminal (16.5 MHz)
59
VSS
—
Ground terminal
60
A1IN
I
Sircs signal input for the CTRL A1 II
61
SIRCS IN
I
SIRCS signal input terminal
62
POWER SW
I
Power switch input terminal
63
RDSCLK
I
RDS serial data transfer clock signal input from the tuner unit
64
MBUS-STS1
I
Strobe control signal input from the sub system controller
65
MBUS-STS2
I
M-BUS status input from the sub system controller
66
MBUS-STS3
I
M-BUS status input from the sub system controller
67
MBUS-STS4
I
M-BUS status input from the sub system controller
68
VCC
—
Power supply terminal (+3.3V)
69
RST TRG
O
Reset signal output to the terminal
70
END FLAG
O
End flag output to the sub system controller
71
A1-LAT
O
Serial data latch pulse output to the sub system controller
72
TUNLAT
O
Serial data latch pulse output to the tuner unit
73
TUNED
I
Tuning detection signal input from the tuner unit
74
STEREO
I
FM stereo detection signal input from the tuner unit
75
TUNDO
I
Serial data input from the tuner unit
76
PREOUT-RY
O
Relay drive signal output terminal Not used
77
VCC
—
Power supply terminal (+3.3V)
78
STOP
I
AC off detection signal input terminal
79
POWRY
O
Relay drive signal output terminal (for main power) “H”: relay on
80
P.CHANGE
O
Tuner auto stop signal output terminal
81
RDSDATA
I
RDS serial data input from the tuner unit
82
PREVOL-LAT
O
Serial data latch pulse output terminal Not used
83
AD/SUB-RST
O
Reset signal output to the sub-2 system controller “L”: rese
84
S-MUTE
O
Muting on/off control signal output terminal
85
SUB-U
CONTROL
O
Clock signal output to the sub-2 system controller
86
SUB-U INFO2
I
Serial data input from the sub-2 system controller
87
SUB-U INFO1
O
Serial data output to the sub-2 system controller
88
FUNCJOG1
I
Jog dial pulse input from the rotary encoder (for INPUT SELECTOR)
89
FUNCJOG2
I
Jog dial pulse input from the rotary encoder (for INPUT SELECTOR)
90
VOLJOG1
I
Jog dial pulse input from the rotary encoder (for MASTER VOLUME)
103
STR-DA5000ES
Pin No.
Pin Name
I/O
Description
91
VOLJOG2
I
Jog dial pulse input from the rotary encoder (for MASTER VOLUME)
92
BASSJOG1
I
Jog dial pulse input from the rotary encoder (for BASS)
93
BASSJOG2
I
Jog dial pulse input from the rotary encoder (for BASS)
94
OSDLAT
O
Serial data latch pulse output to the OSD
95
FLLAT
O
Serial data latch pulse output to the fluorescent display tube
96
FLCLR
O
Clear signal output to the fluorescent display tube
97
VCC
—
Power supply terminal (+3.3V)
98
VSS
—
Ground terminal
99
SDA
I/O
Two-way data bus with the EEPROM
100
SCL
O
Serial data transfer clock signal output to the EEPROM
101
VSS
—
Ground terminal
102
OSD-CLK
O
Serial data transfer clock signal output to the OSD
103
OSD-DAT
O
Serial data output to the OSD
104
OSD-VSINC
I
Not used
105
TREJOG1
I
Jog dial pulse input from the rotary encoder (for TREBLE)
106
TREJOG2
I
Jog dial pulse input from the rotary encoder (for TREBLE)
107
IICDATA
I/O
IIC two-way data bus with the chroma decoder
108
IICCLK
O
IIC bus clock signal output to the choma decoder
109
SOT1
O
Serial data output to the RS-232C
110
SIN1
I
Serial data input from the RS-232C
111
FLCLK
O
Serial data transfer clock signal output to the fluorescent display tube
112
FLDATA
O
Serial data output to the fluorescent display tube
113
DAC-LAT
O
Serial data latch pulse signal output to the D/A converter Not used
114
DAC-RST
O
Reset signal output to the D/A converter “H”: reset Not used
115
DAC-DATA
(UCOM-IN)
I
Serial data input from the D/A converter Not used
116
SP-A
I
Speaker switch input terminal
117
SP-B
I
Speaker switch input terminal
118
MENU JOG1
I
Jog dial pulse input from the rotary encoder (for MENU)
119
MENU JOG2
I
Jog dial pulse input from the rotary encoder (for MENU)
120
PAGE JOG1
I
Jog dial pulse input from the rotary encoder (for MAIN MENU)
121
PAGE JOG2
I
Jog dial pulse input from the rotary encoder (for MAIN MENU)
122
VCC
—
Power supply terminal (+3.3V)
123
LED LAT
O
Serial data latch pulse output to the data decoder/LED driver
124
LED CLR
O
Serial data transfer clock signal output to the data decoder/LED driver
125
PCMSEL
O
Output clock selection signal output to the D-OUT switch
126
DAVS (VSS)
—
Ground terminal (for digital)
127
DAVC (VCC)
—
Power supply terminal (+3.3V) (for digital)
128
AVCC (VCC)
—
Power supply terminal (+3.3V) (for analog)
129
AVRH (VCC)
—
Reference voltage (+3.3V) input terminal (for analog)
130
AVRL (VSS)
—
Ground terminal (for analog)
131
AVSS (VSS)
—
Ground terminal (for analog)
132
AD1
I
Key function A/D input
133
AD2
I
Key function A/D input
134
AD3
I
Key function A/D input
135
VERSION
I
Version set terminal
104
STR-DA5000ES
Pin No.
Pin Name
I/O
Description
136
RDSSIGNAL
I
RDS signal input from the tuner unit
137
HP-SW
I
Headphone detection signal input terminal “H”: headphone is connected
138
+/-JOG1
I
Jog dial pulse input from the rotary encoder (for -/+)
139
+/-JOG2
I
Jog dial pulse input from the rotary encoder (for -/+)
140
VCC2
—
Power supply terminal (+3.3V)
141
BACUP
I
Connected to VCC
142
X0A
O
Not used (Connected to ground)
143
X1A
I
Not used (open)
144
VSS
—
Ground terminal
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