Sony HCD-V909AV / MHC-V909AV Service Manual ▷ View online
— 86 —
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Function
Ground
[MSB]
B input 0–7 (Connect to ground)
[LSB]
Ground
[MSB]
G (Y) input 0–7
[LSB]
Ground
[MSB]
R (Cb/Cr) input 0–7
[LSB]
Power supply (+5V)
Chip select input from IIC interface (IC901)
Serial clock input from IIC interface (IC901)
Serial data input from IIC interface (IC901)
Serial data output. (Not used)
Serial/parallel select
NR effect level control input
NR effect level control input
Block size select input
Power supply (+5V)
RAS signal for DRAM (Connected to ground)
CAS signal for DRAM (Connected to ground)
Write enable signal for DRAM (Connected to ground)
Ground
DRAM data input (Connected to ground)
DRAM data input (Connected to +5V)
DRAM data input (Connected to +5V)
DRAM data input (Connected to ground)
DRAM data input (Not used)
DRAM data input (Connected to +5V)
DRAM data input (Not used)
DRAM data input (Connected to ground)
Ground
Pin Name
V
SS
BI7
BI6
BI5
BI4
BI3
BI2
BI1
BI0
V
SS
Y/GI7
Y/GI6
Y/GI5
Y/GI4
Y/GI3
Y/GI2
Y/GI1
Y/GI0
V
SS
C/RI7
C/RI6
C/RI5
C/RI4
C/RI3
C/RI2
C/RI1
C/RI0
V
DD
XCS
XSCK
SDI
SDO
SXP COM
BLCKNR0
BLCKNR1
BLCKSIZE
V
DD
BLCKST0
BLCKST1
BLCKST2
V
SS
BLOCKST3
CORON
ADVD
ADVS
HVCC
HVCCT
VCP
VCPT
V
SS
I/O
–
I
I
I
I
I
I
I
I
–
I
I
I
I
I
I
I
I
–
I
I
I
I
I
I
I
I
–
I
I
I
O
I
I
I
I
–
I
I
I
–
I
I
I
I
I
I
I
I
–
• IC301 NOISE REDUCTION (CXD1854Q)/VIDEO board
— 87 —
Pin Name
C/RO0
C/RO1
C/RO2
C/RO3
C/RO4
C/RO5
C/RO6
C/RO7
V
DD
Y/GO7
Y/GO6
Y/GO5
Y/GO4
Y/GO3
Y/GO2
Y/GO1
Y/GO0
V
DD
BO0
BO1
BO2
BO3
BO4
BO5
BO6
BO7
V
SS
HSYO
VSYO
CBLO
CSYO
HAPGAIN0
HAPGAIN1
TEST
TEN
HAPBPF0
IFSEL 1
HAPBPF1
NRON
LEVEL 0
LEVEL 1
FNR UFRZ
XRST
V
SS
CSYI
CBLI
VSYI
HSYI
V
DD
DCLKI
Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
I/O
O
O
O
O
O
O
O
O
–
O
O
O
O
O
O
O
O
–
O
O
O
O
O
O
O
O
–
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
–
I
I
I
I
–
I
Function
[MSB]
R (Cb/Cr) output 0–7
[LSB]
Power supply (+5V)
[MSB]
G (Y) output 0–7
[LSB]
Power supply (+5V)
[MSB]
B output 0–7 (Not used)
[LSB]
Ground
H SYNC output (Not used)
V SYNC output (Not used)
Composit blanking output (Not used)
Composit SYNC output (Not used)
Profile cooperation effect level control
Profile cooperation effect level control
Test pin (Connect to ground)
Test pin (Connect to +5V)
Profile cooperation correction band control
Matrix select Y/C, RGB (Connect to ground)
Profile cooperation correction band control
Noise reducer on/off (Not used)
Noise reducer level select
0: weak –3: strong (Not used)
NR feedback coefficient deser processor select (Connect to +5V)
Power on reset
Ground
Composit SYNC input (Connect to ground)
Composit blanking input (Connect to +5V)
V SYNC input
H SYNC input
Power supply (+5V)
Dot clock input (13.5MHz)
— 88 —
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
• IC401 10 BIT VIDEO D/A CONVERTER (CXD1913Q)/VIDEO board
Pin Name
Y7
Y6
Y5
Y4
V
SS
Y3
Y2
Y1
Y0
V
DD
C7
C6
C5
C4
C3
C2
C1
C0
V
SS
IREF
VREF
AV
DD
1
AV
SS
1
COMPO
VB
VG
AV
DD
2
AV
SS
2
YOUT
AV
DD
3
AV
SS
3
COUT
TD10
V
DD
I/O
I
I
I
I
–
I
I
I
I
–
I
I
I
I
I
I
I
I
–
O
I
–
–
O
I
I
–
–
O
–
–
O
O
–
Function
8-bit pixel data input pins (PD0 to 7).
When control register bit “PIF MODE”=“0”, serve as input pins for multiplexed Y, Cb, Cr
signals.
When control register bit “PIF MODE”=“1”, serve as input pins for Y signal
Digital ground
8-bit pixel data input pins (PD0 to 7).
When control register bit “PIF MODE”=“0”, serve as input pins for multiplexed Y, Cb, Cr
signals.
When control register bit “PIF MODE”=“1”, serve as input pins for Y signal
Digital power supply
8-bit pixel data input pins/test data bus.
When control register bit “PIF MODE”=“0”, these input pins cannot be used.
When control register bit “PIF MODE”=“1”, serve as input pins for multiplexed Cb, Cr
signals.
In the test mode, used for internal circuit test data bus.
The test mode is allowed to use only for device vendors
Digital ground
Reference current output pin.
Connect a resistor
×
16 times (“16R”) of the output resistance value “R”
Voltage reference input pin.
Sets the output full-scale value
Analog power supply
Analog ground
10-bit D/A converter output.
When control register bit “YC/YUV”=“1”, outputs the composite signal.
When control register bit “YC/YUV”=“0”, outputs the color difference (V) signal
Connect to Vss with an approx. 0.1 µF capacitor
Connect to AV
DD
with an approx. 0.1 µF capacitor
Analog power supply
Analog ground
10 bit D/A converter output.
(Luminance (Y) signal output.)
Analog power supply
Analog ground
10-bit D/A converter output.
When control register bit “YC/YUV”=“1”, outputs the chroma (C) signal.
When control register bit “YC/YUV”=“0”, outputs the color difference (U) signal
Test data bus.
In the test mode, used for internal circuit test data bus.
The test mode is allowed to use only for device vendors (Not used)
Digital power supply
— 89 —
Pin Name
TD9
TD8
XTEST1
XTEST2
XTEST3
V
SS
TRST
V
DD
TDI
TMS
TCK
TDO
V
SS
SI
SCK
XCS
XVRST
F1
V
DD
XTEST4
XRST
SYSCLK
Pin No.
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
I/O
O
O
I
I
I
–
I
–
I
I
I
O
–
I
I
I
I
I
–
I
I
I
Function
Test data bus.
In the test mode, used for internal circuit test data bus.
The test mode is allowed to use only for device vendors (Not used)
Test mode control input pin. Pulled-up.
When these pins are “H”, CXD1913Q is not in the test mode.
The test mode is allowed to use only for device vendors
Digital ground
Test mode reset input pin.
During power on/reset, set to “L” for more than 40 clocks (SYSCLK) (Not used)
Digital power supply
Test mode control input pin. (Not used)
Test mode control input pin. Fix at “H”
Test data bus pin. (Not used)
Digital ground
The functions of this pin are selected by Pin 64 XIICEN.
When the XIICEN pin is “H”, sets into the SONY SIO mode, and becomes the SI serial
data input pin.
When the XIICEN pin is “L”, sets into the I
2
C-BUS mode, and becomes the SDA input/
output pin
The functions of this pin are selected by Pin 64 XIICEN.
When the XIICEN pin is “H”, sets into the SONY SIO mode, and becomes the SCK serial
clock input pin.
When the XIICEN pin is “L”, sets into the I
2
C-BUS mode, and becomes the SCL input pin
The functions of this pin are selected by Pin 64 XIICEN. Pulled-up.
When the XIICEN pin is “H”, sets into the SONY SIO mode, and becomes the XCK chip
select input pin.
When the XIICEN pin is “L”, sets into the I
2
C-BUS mode, and becomes the SA slave
address selection input signal which selects the I
2
C-BUS slave address
Active “L” vertical sync reset input pin. Pulled-up.
Used for synchronizing external vertical sync and internal vertical sync.
When XVRST is “L”, the internal digital sync generator is reset according to the F1 state
Field ID input pin.
When externally synchronizing with the XVRST signal, the field to be reset is determined
by this signal.
“H” indicates the first field.
“L” indicates the second field
Digital power supply
Test mode control input pin. Pulled-up.
When these pins are “H”, CXD1913Q is not s test mode.
The test mode is allowed to use only for device vendors
System reset input pin when active “L”.
During power on/reset, set to “L” for more than 40 clocks (SYSCLK)
System clock input pin.
To generate the correct sub carrier frequency, precisely 27MHz is required
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