Sony HCD-V909AV / MHC-V909AV Service Manual ▷ View online
— 78 —
1
5
6
+
–
+
20
19
18
17
16
15
14
13
21
22
23
24
2
3
4
7
8
9
10
12
11
+
DEC
IN-FILTER
(40kHz)
VDD
ADM-CONT
SRAM
ADM
OUT-FILTER
(7k/5k)
B-NR
DC-OUT
VOL/MUTE
S-TRIM
INV-PHASE
R+DELAY
L+DELAY
A
B
A
B
A
B
A
B
A
B
A
B
A
B
L–R
L+R
(–6dB)
A
B
A.GND
L-OUT
R-OUT
VREF
S-OUT
DELAY-OUT
S-IN
R-IN
L-IN
VCC
NR-DET
ENABLE
DATA
CLK
D.GND
DC-CUT
VDD
OSC
OSC
NR-IREF
DC-CUT
IC602 LV1016
• Deck section
IC402 LB1641
1
2
3
4
5
6
7
8
9
10
GND
MOTOR
DRIVE
NOISE
FILTER
CLAMP
FWD.IN
REV.IN
VCC 1
VCC 2
NOISE
FILTER
MOTOR
DRIVE
MOTOR
DRIVE
MOTOR
DRIVE
T.S.D
O.C.P
FWD/REV/STOP
CONTROL LOGIC
IC602 uPC1330HA
1
2
3
4
5
6
7
8
9
INVERTER
COMPARATER
SW R1
GND
SW P1 CONT
GND
VCC
SW P2 GND
SW R2
• Panel section
IC751 M65850P
• Power section
IC301 uPC1237HA
1
2
3
4
5
6
7
8
OVER LOAD DET
F/F
OFFSET DET
LATCH/
AUTORESET
V
CC
ON
MUTE
AC OFF
DET
V
CC
OSCILLATOR
1/2 VCC
AUTO
RESET
LPF1
MAIN
CONTROL
A/D
20KBIT
SRAM
LPF2
D/A
1
2
3
4
5
6
7
8
9
10
14
13
12
11
CLOCK
RESET
MO
MI
D1
DO0
DO1
VCC
CLOCK
REF
OP2IN
OP2OUT
LPF2IN
LPF2OUT
LPF1IN
LPF1OUT
OP1OUT
OP1IN
CC1
CC2
GND
— 79 —
• CD motor section
IC701 M54641L
• KEY CON section
IC1401 M65847FP
1
2
3
4
5
6
7
8
ADCONT
DA1CONT
KEY DOWN
KEY UP
DAIINTIN
ADINTOUT
ADINTIN
LPF1
REF
REF
REF
REF
HPF
LPF2
MIX
CLKO/KEY0
SDATA/KEY1
SCK/KEY2
STROBE/KEY3
KEY4
KEY5
REF
GND
VCC
MODE2
MODE1
DAIINTOUT
LPF1IN
LPF1OUT
HPFIN
HPFOUT
LPF2IN
LPF2OUT
MIXIN
MIXOUT
DA2CONT
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
+
–
LOGIC
D/A
RESET
RAM
A/D
CLOCK
GENERATOR
REF
+
–
+
–
+
–
1
2
3
4
5
6
7
8
B1
B0
C.COM
CO
INH
VEE
VSS
VDD
B.COM
A.COM
A1
A0
A
B
C
C1
9
10
11
12
13
14
15
16
OPEN
OPEN
OPEN
IC1403 MC14053BCP
1
5
2
7
3
6
4
POWER
AMP.
AMP.
POWER
AMP.
AMP.
CONTROL
INPUT
AMP.
INPUT
AMP.
REG
8
VCC
VCC
REFERENCE
OUT2
OUT1
IN1
IN2
GND
IC801 BA6286N
1
2
3
2
3
4
5
6
5
6
7
8
9
8
9
10
TSD
CONTROL
LOGIC
PO WER
SAVE
GND
RIN
VREF
OUT2
OUT2
RNF
GND
VM
VCC
FIN
OUT1
— 80 —
7-20. IC PIN FUNCTIONS
• IC101 DIGITAL SIGNAL PROCESSOR (CXD2545Q)/BD board
Pin Name
SRON
SRDR
SFON
TFDR
TRON
TRDR
TFON
FFDR
FRON
FRDR
FFON
VCOO
VCOI
TEST
DV
SS
TES2
TES3
PDO
VPCO
VCKI
AVD2
IGEN
AVS2
ADIO
RFC
RFDC
TE
SE
FE
VC
FILO
FILI
PCO
CLTV
AVS1
RFAC
BIAS
ASYI
ASYO
AVD1
DV
DD
ASYE
PSSL
WDCK
LRCK
DATA
BCLK
64DATA
64BCLK
64LRCK
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I/O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
–
I
I
O
O
I
–
I
–
I
O
I
I
I
I
I
O
I
O
I
–
I
I
I
O
–
–
I
I
O
O
O
O
O
O
O
Function
Sled drive output (Not used)
Sled drive output
Sled drive output (Not used)
Tracking drive output
Tracking drive output (Not used)
Tracking drive output
Tracking drive output (Not used)
Focus drive output
Focus drive output (Not used)
Focus drive output
Focus drive output (Not used)
VCO output for analog EFM (Eight to Fourteen Modulation) PLL (Not used)
VCO input from analog EFM PLL (Ground)
TEST pin connected normally to ground
Digital ground
TEST pin connected normally to ground
TEST pin connected normally to ground
Charge-pump output for analog EFM PLL (Not used)
Charge-pump output for variable pitch PLL (Not used)
Clock input from variable pitch external VCO (Ground)
Analog power supply
Power supply pin for operational amplifiers
Analog ground
(Not used)
(Not used)
RF signal input
Tracking error signal input
Sled error signal input
Focus error signal input
Center voltage input pin
Filter output for master PLL
Filter input for master PLL
Charge-pump output for master PLL
Control voltage input for master VCO
Analog ground
EFM signal input
Asymmetry circuit constant current input
Asymmetry comparate voltage input
EFM full swing output
Analog power supply
Digital power supply
Asymmetry circuit ON/OFF
Audio data output mode selection input
48-bit slot D/A interface. word clock.
48-bit slot D/A interface. LR clock.
DA 16 output when PSSL=1. 48-bit slot serial data when PSSL=0
DA 15 output when PSSL=1. 48-bit slot data when PSSL=0
DA 14 output when PSSL=1. 64-bit slot data when PSSL=0 (Not used)
DA 13 output when PSSL=1. 64-bit slot data when PSSL=0 (Not used)
DA 12 output when PSSL=1. 64-bit slot data when PSSL=0 (Not used)
— 81 —
Pin Name
GTOP
XUGF
XPLCK
GFS
PFCK
C2PO
XRAOF
MNT3
MNT2
MNT1
MNT0
XTAI
XTAO
XTSL
DV
SS
FSTI
FSTO
FSOF
C16M
MD2
DOUT
EMPH
WFCK
SCOR
SBSO
EXCK
SUBQ
SQCK
MUTE
SENS
XRST
DIRC
SCLK
DFSW
ATSK
DATA
XLAT
CLOK
COUT
DV
DD
MIRR
DFCT
FOK
FSW
MON
NDP
MDS
LOCK
SSTP
SFDR
I/O
O
O
O
O
O
O
O
O
O
O
O
I
O
I
–
I
O
O
O
I
O
O
O
O
O
I
O
I
I
O
I
I
I
I
I
I
I
I
O
–
O
O
O
O
O
O
O
O
I
O
Function
DA 11 output when PSSL=1. GTOP output when PSSL=0 (Not used)
DA 10 output when PSSL=1. XUGF output when PSSL=0 (Not used)
DA 09 output when PSSL=1. XPLCK output when PSSL=0
DA 08 output when PSSL=1. GFS output when PSSL=0
DA 07 output when PSSL=1. RFCK output when PSSL=0
DA 06 output when PSSL=1. C2PO output when PSSL=0 (Not used)
DA 05 output when PSSL=1. XRA0F output when PSSL=0
DA 04 output when PSSL=1. MNT3 output when PSSL=0
DA 03 output when PSSL=1. MNT2 output when PSSL=0
DA 02 output when PSSL=1. MNT1 output when PSSL=0
DA 01 output when PSSL=1. MNT0 output when PSSL=0
X’tal oscillator circuit input
X’tal oscillator circuit output (Not used)
X’tal selection input pin (Ground)
Digital ground
2/3 divider input of pins 62, 63
2/3 divider output of pins 62, 63
(Not used)
16.9344 MHz output (Not used)
Digital-out ON/OFF control pin (+5V)
Digital-out output pin
Playback disc output in emphasis mode (Not used)
WFCK (Write Frame Clock) output
Sub-code sync output
Sub-P through Sub-W serial output (Not used)
Clock input for SBSO read-out (Ground)
Sub-Q 80-bit output
Clock input for SQSO read-out
Muting selection pin
SENS output
System reset
Used in 1-track jump mode (+5V)
SENS serial data read-out clock
Defect selection pin (Ground)
Input pin for anti-shock (Ground)
Serial data input, supplied from CPU
Latch input, supplied from CPU
Serial data transfer clock input, supplied from CPU
Numbers of track counted signal output (Not used)
Digital power supply
Mirror signal output
Defect signal output (DFCT: Defect)
Focus OK output
Output to select spindle motor output filter (Not used)
Output to control ON/OFF of spindle motor (Not used)
Output to control spindle motor servo
Output to control spindle motor servo (Not used)
GFS (Guarded Frame Sync) is sampled by 460 Hz. H when GFS is H (Not used)
Input signal to detect disc inner most track
Sled drive output
Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Click on the first or last page to see other HCD-V909AV / MHC-V909AV service manuals if exist.