Sony HCD-V909AV / MHC-V909AV Service Manual ▷ View online
— 82 —
• IC201 MPEG DECODER (CXD1852AQ)/VIDEO board
Pin Name
V
SS
XTL0O
XTL0I
V
DD
HA2
HA3
HD0
HD1
HD2
HD3
HD4
HD5
HD6
V
DD
V
SS
HD7
MA3
MA4
MA2
MA5
MA1
V
SS
MA6
MA0
BC
TCKI
TDI
TENAI
TDO
VST
V
SS
MA7
MA8
XRAS
XMWE
XCAS2
/MA9
XCAS0
MD7
MD8
MD6
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
I/O
–
O
I
–
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
–
–
I/O
O
O
O
O
O
–
O
O
I
I
I
I
I
I
–
O
O
O
O
O
O
I/O
I/O
I/O
Function
Ground
Video decoder master clock pin. Input the XTL0I clock or connect an oscillator between
XTL0I and XTL0O. The recommended frequencies are 27MHz, 28.6363MHz (NTSC
8fsc), and 35.4686 MHz (PAL 8fsc).
+5V power supply
Address input pin. In some cases, serves as the control signal and data input according to
the setting of the control mode.
Data input/output
+5V power supply
Ground
Data input/output
Address signal pin. Connect to the DRAM address pin with the same number.
Ground
Address signal pin. Connect to the DRAM address pin with the same number.
For test (Not used)
For test (Connect to ground)
Ground
Address signal pin. Connect to the DRAM address pin with the same number.
RAS signal pin. Connect to the RAS pin of the DRAM. Same for the 256Kw
×
16b,
256Kw
×
16b
×
2, and 512Kw
×
8b
×
2 DRAM structures.
WE signal pin. Connect to the WE pin of the DRAM.
CAS signal. Connect to the CAS pin of the DRAM so as to control the lower bytes of the
upper word (256K to 512K-1) for the 256Kw
×
16b
×
2 DRAM structure. / Address signal
pin. Connect to the DRAM address pin with the same number. (Not used)
CAS signal. Connect to the CAS pin of the DRAM so as to control the lower bytes (MD0
to MD7) for 256Kw
×
16b and 512Kw
×
8b
×
2 DRAM structures, and to control the
lower bytes of the lower word (0 to 256K-1) for the 256Kw
×
16b
×
2 DRAM structure.
Data input/output signal pin. Connect to the DRAM data pin so that the lower and upper
bytes of the data correspond to the CAS0 to CAS3 controls.
— 83 —
I/O
I/O
I/O
I/O
–
–
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
–
–
I
O
O
O
O
O
O
O
O
O
O
O
–
–
O
O
O
O
O
Function
Data input/output signal pin. Connect to the DRAM data pin so that the lower and upper
bytes of the data correspond to the CAS0 to CAS3 controls.
+5V power supply
Ground
Data input/output signal pin. Connect to the DRAM data pin so that the lower and upper
bytes of the data correspond to the CAS0 to CAS3 controls.
OSD enable signal
OSD data input pin. When the XOSDEN input is “L”, the color registered in the register
specified by this 3 inputs (3 bits) is output as the image data.
+5V power supply
Ground
Video output enable signal pin. When set to “L”, enables the image data output and DCLK
output. When set to “H”, disables (high impedance). Output control can also be performed
by writing in the register. (Connected to ground)
Output pin of the R or Cr signal of the image data. MSB is R/Cr7. Synchronizes with
DCLK.
Output pin of the G or Y signal of the image data. MSB is G/Y7. Synchronizes with
DCLK.
+5V power supply
Ground
Output pin of the G or Y signal of the image data. MSB is G/Y7. Synchronizes with
DCLK.
Pin Name
MD9
MD5
MD10
V
DD
V
SS
MD4
MD11
MD3
MD12
MD2
MD13
MD1
MD14
MD0
MD15
XOSDEN
OSDB
OSDG
OSDR
V
DD
V
SS
XVOE
R/Cr0
R/Cr1
R/Cr2
R/Cr3
R/Cr4
R/Cr5
R/Cr6
R/Cr7
G/Y0
G/Y1
G/Y2
V
DD
V
SS
G/Y3
G/Y4
G/Y5
G/Y6
G/Y7
Pin No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
— 84 —
Pin No.
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
I/O
O
O
O
O
O
O
O
O
I
–
–
I
I
I
I
O
I
O
O
O
O
O
I
–
–
O
I
–
I
I
Function
Output pin of the B or Cb signal of the image data. MSB is B/Cb7. Synchronizes with
DCLK. (Not used)
Dot clock (DCLK) signal pin. The DCLK frequency is normally 13.5MHz. The DCLK can
be input from this pin or can be made by frequency-dividing (1/integer) the clock input
from XTL0I.
+5V power supply
Ground
Horizontal sync signal pin. When using the built-in sync generator, a signal is made by
frequency-dividing the dot clock (DCLK). Serves as the input when not using the built-in
sync generator.
Vertical sync signal pin. When using the built-in sync generator, a signal is made by fre-
quency-dividing the DCLK. Serves as the input when not using the built-in sync generator.
Field determination signal. Odd field correspond to “H” and even field correspond to “L”.
Serves as an output when the built-in sync generator is used, and as an input when not.
/ Signal obtained by frequency-dividing the clock input from XTL0I or XTLI. When the
input clock is 8 fsc, it can be used as the horizontal sync signal phase comparison reference
signal.
Composite blanking signal pin. Serves as an output when the built-in sync generator is
used, and as an input when not. / Signal obtained by frequency-dividing the clock input
from XTL0I or XTLI. When the input clock is 8 fsc, it can be used as the fsc signal.
Composite sync signal pin. A signal is made by frequency-dividing the DCLK. Cannot be
input. (Not used)
Sync generator reset signal pin. The signal generator is initialized by setting this pin to “L”.
Outputs the frequency-divided clock of the clock input to XTL0I. The frequency dividing
ratio can be selected from 1/2, 1/4, and 1/8. (Not used)
Digital output (Not used)
Audio serial data output to Audio D/A converter (IC101)
LR clock output to Audio D/A converter (IC101)
Bit clock output to Audio D/A converter (IC101)
Input 384fs (16.9344MHz) or 768fs (33.8688MHz).
+5V power supply
Ground
CD-ROM decoder, audio decoder master clock. Input a clock to the XTL21 or connect an
oscillator between XTL2I and XTL2O. The recommended frequency is 45 MHz. This
clock is for the internal circuit. Does not synchronize with inputs and outputs.
+5V power supply
C2 pointer input (CXD2545Q)
LR clock input (CXD2545Q)
Pin Name
B/Cb0
B/Cb1
B/Cb2
B/Cb3
B/Cb4
B/Cb5
B/Cb6
B/Cb7
DCLK
V
DD
V
SS
HSYNC
VSYNC
FID
/FHREF
CBLNK
/FSC
CSYNC
XSGRST
CLK0O
DOUT
DATO
LRCO
BCKO
FSXI
V
DD
V
SS
XTL2O
XTL2I
V
DD
C2PO
LRCI
— 85 —
Pin Name
DATI
BCKI
DOIN
XHCS
XHDT
HRW
XHIRQ
XRST
HA0
HA1
Pin No.
111
112
113
114
115
116
117
118
119
120
I/O
I
I
I
I
I/O
I
O
I
I
I
Function
Serial data input (CXD2545Q)
Bit clock input (CXD2545Q)
Digital input signal (Not used)
Register access chip select signal pin.
Data acknowledge/wait signal pin for DMA transmission, register access, transparent
memory access.
Register access control signal pin.
Interrupt request signal
Hardware reset input pin. When set to “L”, all registers and operations are reset and initialized.
Address input pin. In some cases, serves as the control signal and data input according to
the setting of the control mode.
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