Sony HCD-FR1K / HCD-FR8 / HCD-FR9 (serv.man2) Service Manual ▷ View online
29
HCD-FR1/FR8/FR9
IC907 PST3645NR
VREF
5
4
3
2
1
OUT
VDD
GND
NC
CD
– RELAY Board –
IC701, 711, 721 BA6956AN
1
2
3
4
5
6
7
8
9
CONTROL LOGIC
TSD
VREF
OUT2
OUT1
RNF
VM
VCC
FIN
GND
RIN
IC812, 813 SN74LV245APWR
1
2
3
4
5 6
7
8
9
10
20 19 18 17 16 15 14 13 12 11
A1
DIR
A2
A3
A4
A5
A6
A7
A8
GND
ENABLE
G
V
CC
B1
B2
B3
B4
B5
B
l
B7
B8
IC814 TC7WH157FK (TE85R)
SELECT
11
6
ST
11
7
A
1
2
3
A
B
Y
5
Y
B
GND 4
VCC
8
Y
EN G
Y
30
HCD-FR1/FR8/FR9
IC602 MC14052 BDR2
IC605
M62429FP-TP
VR 2
VR 1
VIN1
VOUT1
GND
DATA
VIN2
VOUT2
VCC
CLOCK
7
2
3
4
8
1
REF AMP
VOL AMP 2
VOL AMP 1
6
LOGIC
CONTROL
5
VREF
IC201
MM1623BFBE
1
VCC1
2
C IN
3
MUTE 1
4
CVBS IN
28 VCC2
23 CVBS OUT
25 S1
150k
Ω
BIAS
12
CB IN
150k
Ω
BIAS
CLAMP
6dB
6dB
6
Y IN
7
GND
8
BIAS
CLAMP
BIAS
6dB
9
I/P
10
CY IN
11
CLP
13
MUTE2
5
YC MIX
+
6dB
–6dB
6dB
27 S-DC OUT
24 S2
LOW-PASS
FILTER
21 Y OUT
22 GND2
6.75MHz
75
Ω
DRIVER
LOW-PASS
FILTER
6.75MHz
75
Ω
DRIVER
20 CY OUT
75
Ω
DRIVER
S-DC OUT
S1/S2
26 C OUT
LOW-PASS
FILTER
6.75MHz
75
Ω
DRIVER
CLAMP
150k
Ω
BIAS
LOW-PASS
FILTER
6.75MHz
LOW-PASS
FILTER
13.5MHz
18 CB OUT
19 GND2
17 GND2
15 GND2
75
Ω
DRIVER
LOW-PASS
FILTER
6.75MHz
LOW-PASS
FILTER
13.5MHz
14
CR IN
150k
Ω
BIAS
16 CR OUT
75
Ω
DRIVER
LOW-PASS
FILTER
6.75MHz
LOW-PASS
FILTER
13.5MHz
6dB
6dB
– IO Board –
31
HCD-FR1/FR8/FR9
– RF Board –
IC001
CXD1881AR
MUX
ATT
INPUT
BIAS
AGC
GCA
PROGRAMMABLE
EQUALIZER
FILTER
DIFFERENTIATOR
64 63
62 61 60 59
58
57
51
56
1
2
FULL WAVE
RECTIFER
AGC CHARGE
PUMP
+
–
+
–
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
–
–
+
–
–
+
–
–
INPUT
SEL
ATT
2
4
2
2
INPUT
IMPEDANCE
SEL
OFFSET
CANSEL
MNTR
CONTROL
SERIAL
PORT
REGISTER
4
FROM
S-PORT
4
FROM
S-PORT
INPUT
IMPEDANCE
SEL
3
FROM
S-PORT
CLAMP &
ENVELOPE
LEVEL
DAC
SIGDET
AGCO
BUFFER
55 54
53 52
50
49
OUTPUT
INHIBIT
FROM S-PORT
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
GCA
CD/DVD
4
FROM
S-PORT
3
FROM
S-PORT
MUX
3
FROM
S-PORT
GCA
3
FROM
S-PORT
3
FROM
S-PORT
EQ
VC
COMPARATOR
PHASE
DETECTOR
PHASE
DETECTOR
A+D
B+D
+
+
+
A+C
B+C
GCA
W/LPF
SUM
AMP
AMP
18 19 20
21 22
24 25
23
26
27
28 29
31
32
30
GCA
GCA
VCI FOR SERVO INPUT
VC = VPB/2
DUAL APC
LD H/L
FROM S-PORT
APC SEL
DVD/CD
TOPHOLD
GCA
TOPHOLD
GCA
41
48
47
46
45
GCA
OFFSET
CANSEL
5
FROM
S-PORT
GCA
40
GCA
OFFSET
CANSEL
6
FROM
S-PORT
3
FROM
S-PORT
GCA
GCA
CEFDB
CP/CN
LOW
IMPEDANCE
CD/DVD
SUB
GCA
MUX
GCA
LPF
GCA
LPF
39
38
37
36
OFFSET
CANSEL
PEAK/BOTTOM
HOLD
BOTTOM
ENVELOPE
INPUT
BUFFER
5
FROM
S-PORT
GCA
LPF
V25/2
TE
RST
35
34
33
FOR SERVO
OUTPUT
PH
TOP
HOLD
GCA
SEL
LINKEN
MUX
HOLDEN
+
–
+
–
COMPA-
RATOR
INTERNAL
FDGHG
HYSTERESISTER
& OFFSET
FROM S-PORT
MIRR
COMPARATOR
COMPARATOR
INPUT GAIN
FROM S-PORT
SEL
DAC
SINK CURRENT
FROM S-PORT
2
AGCO
FAST ATTACK
AGC
HOLD
BCA
DET
DET
2
FROM
S-PORT
PH
2
2
INPUT
IMPEDANCE
FROM S-PORT
44
43
42
V33 FOR
OUTPUT
OUTPUT
BUFFER
PI
FE
TE
CE
V25
V125
V25/3
LPF ATT
POL SEL
BUFFER
CONTROL
SIGNALS
TO EACH
BLOCK
3
CE ATT
CEPOL
D
C
B
A
CD F
VPB
VC
DVDLD
CDLD
CDPD
DVDPD
LDON
VNB
MIRR
MP
MB
MIN
MEVO
MLPF
CE
SDEN
SDATA
SCLK
V33
FE
TE
PI
V25
V125
TPH
DFT
LINK
LPC
LCN
MNTR
DVDRFP
DVDRFN
A2
B2
C2
D2
CP
CN
D
C
B
A
CD D
CD C
CD B
CD A
RFDC
RFSIN
A
TOP
A
TON
AIN
AIP
VP
A
RF
AC
VNA
BYP
DIN
DIP
FNP
FNN
MEV
RX
CD E
32
HCD-FR1/FR8/FR9
• IC Pin Function Description
DMB08 BOARD IC206 ZIVA5X-C2F (DVD SYSTEM PROCESSOR)
DMB08 BOARD IC206 ZIVA5X-C2F (DVD SYSTEM PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
VDDP
—
Power supply terminal (+3.3V) (I/O signal)
2
HA1
I/O
Address bus
3
HD15
I/O
Data bus (address signal multiplexed)
4
HD14
I/O
Data bus (address signal multiplexed)
5
HD13
I/O
Data bus (address signal multiplexed)
6
HD12
I/O
Data bus (address signal multiplexed)
7
HD11
I/O
Data bus (address signal multiplexed)
8
HD10
I/O
Data bus (address signal multiplexed)
9
HD9
I/O
Data bus (address signal multiplexed)
10
HD8
I/O
Data bus (address signal multiplexed)
11
HD7
I/O
Data bus (address signal multiplexed)
12
VDDP
—
Power supply terminal (+3.3V) (I/O signal)
13
GNDP
—
Ground terminal (I/O signal)
14
HD6
I/O
Data bus (address signal multiplexed)
15
HD5
I/O
Data bus (address signal multiplexed)
16
HD4
I/O
Data bus (address signal multiplexed)
17
HD3
I/O
Data bus (address signal multiplexed)
18
HD2
I/O
Data bus (address signal multiplexed)
19
HD1
I/O
Data bus (address signal multiplexed)
20
VDDP
—
Power supply terminal (+3.3V) (I/O signal)
21
GNDP
—
Ground terminal (I/O signal)
22
HD0
I/O
Data bus (address signal multiplexed)
23
HDTACK
I/O
Acknowledge signal input/output for host data transfer (not used)
24
HIRQ0
I
Interrupt signal input for Medusa (not used)
25
WEH.UDS
I/O
Host upper data strobe signal output
26
WEL.LDS
I/O
Host lower data strobe signal output (not used)
27
HREAD
I/O
Read/write strobe signal output
28
GPIO0
I/O
Jig detection port (pull-up)
29
GND
—
Ground terminal (inside core)
30
VDD
—
Power supply terminal (+1.8V) (inside core)
31
GND25
—
Ground terminal (SDRAM I/O signal)
32
VDD25
—
Power supply terminal (+3.3V) (SDRAM I/O signal)
33
MA9
O
SDRAM address bus
34
MA8
O
SDRAM address bus
35
MA7
O
SDRAM address bus
36
MA6
O
SDRAM address bus
37
MA5
O
SDRAM address bus
38
MA4
O
SDRAM address bus
39
MA3
O
SDRAM address bus
40
MA2
O
SDRAM address bus
41
MA1
O
SDRAM address bus
42
MA0
O
SDRAM address bus
43
GND25
—
Ground terminal (SDRAM I/O signal)
44
VDD25
—
Power supply terminal (+3.3V) (SDRAM I/O signal)
45
MA10
O
SDRAM address bus
46
MA11
O
SDRAM address bus
47
BA1
O
SDRAM bank select 1 signal output
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