Sony HCD-FR1K / HCD-FR8 / HCD-FR9 (serv.man2) Service Manual ▷ View online
33
HCD-FR1/FR8/FR9
Pin No.
Pin Name
I/O
Description
48
BA0
O
SDRAM bank select 0 signal output
49
MCS0
O
SDRAM chip select 0 signal output
50
MCS1
O
Not used
51
MRAS
O
SDRAM row address strobe signal output
52
MCAS
O
SDRAM column address strobe signal output
53
MWE
O
SDRAM write enable signal output (“H” : read, “L” : write)
54
GND25
—
Ground terminal (SDRAM I/O signal)
55
VDD25
—
Power supply terminal (+3.3V) (SDRAM I/O signal)
56
MCLK
O
SDRAM Clock output
57
MD0
I/O
SDRAM data
58
MD1
I/O
SDRAM data
59
MD2
I/O
SDRAM data
60
MD3
I/O
SDRAM data
61
GND25
—
Ground terminal (SDRAM I/O signal)
62
MDQM0
O
Byte read /write mask signal 0 output
63
VDD25
—
Power supply terminal (+3.3V) (SDRAM I/O signal)
64
MD4
I/O
SDRAM data
65
MD5
I/O
SDRAM data
66
MD6
I/O
SDRAM data
67
MD7
I/O
SDRAM data
68
MD8
I/O
SDRAM data
69
MD9
I/O
SDRAM data
70
MD10
I/O
SDRAM data
71
MD11
I/O
SDRAM data
72
GND25
—
Ground terminal (SDRAM I/O signal)
73
MDQM1
O
Byte read /write mask signal 1 output
74
VDD25
—
Power supply terminal (+3.3V) (SDRAM I/O signal)
75
MD12
I/O
SDRAM data
76
MD13
I/O
SDRAM data
77
MD14
I/O
SDRAM data
78
MD15
I/O
SDRAM data
79
GND
—
Ground terminal (inside core)
80
VDD
—
Power supply terminal (+1.8V) (inside core)
81
MD16
I/O
SDRAM data
82
MD17
I/O
SDRAM data
83
MD18
I/O
SDRAM data
84
MD19
I/O
SDRAM data
85
GND25
—
Ground terminal (SDRAM I/O signal)
86
MDQM2
O
Byte read /write mask signal 2 output
87
VDD25
—
Power supply terminal (+3.3V) (SDRAM I/O signal)
88
MD20
I/O
SDRAM data
89
MD21
I/O
SDRAM data
90
MD22
I/O
SDRAM data
91
MD23
I/O
SDRAM data
92
MD24
I/O
SDRAM data
93
MD25
I/O
SDRAM data
94
MD26
I/O
SDRAM data
34
HCD-FR1/FR8/FR9
Pin No.
Pin Name
I/O
Description
95
MD27
I/O
SDRAM data
96
GND25
—
Ground terminal (SDRAM I/O signal)
97
MDQM3
O
Byte read /write mask signal 3 output
98
VDD25
—
Power supply terminal (+3.3V) (SDRAM I/O signal)
99
MD28
I/O
SDRAM data
100
MD29
I/O
SDRAM data
101
MD30
I/O
SDRAM data
102
MD31
I/O
SDRAM data
103
GND25
—
Ground terminal (SDRAM I/O signal)
104
VDD25
—
Power supply terminal (+3.3V) (SDRAM I/O signal)
105
VCLK
I/O
System clock (not used)
106
I2C_CTRL
—
Not used
107
VS
O
S1 signal output
108
I/P SW
O
Progressive/interlace switch signal output (not used)
109
GPIO1 (5)
—
Not used
110
GPIO1 (4)
—
Not used
111
VDDP
—
Power supply terminal (+3.3V) (I/O signal)
112
GNDP
—
Ground terminal (I/O signal)
113
GPIO1 (3)
—
Not used
114
GPIO1 (2)
—
Not used
115
GPIO1 (1)
—
Not used
116
HIRQ2_
I
Busy signal input from the EEPROM (IC203)
117
VDAC_4B
—
Video DAC bias bit 4 (connected to the ground)
118
VDAC_VDD4
—
Power supply terminal (+3.3V) (Video DAC 4)
119
VDAC_4
O
VDAC output 4
120
VDAC_3B
—
Video DAC bias bit 3 (connected to the ground)
121
VDAC_VDD3
—
Power supply terminal (+3.3V) (Video DAC 3)
122
VDAC_3
O
VDAC output 3
123
VDAC_2B
—
Video DAC bias bit 2 (connected to the ground)
124
VDAC_VDD2
—
Power supply terminal (+3.3V) (Video DAC 2)
125
VDAC_2
O
VDAC output 2
126
VDAC_1B
—
Video DAC bias bit 1 (connected to the ground)
127
VDAC_VDD1
—
Power supply terminal (+3.3V) (Video DAC 1)
128
VDAC_1
O
VDAC output 1
129
VDAC_0B
—
Video DAC bias bit 0 (connected to the ground)
130
VDAC_VDD0
—
Power supply terminal (+3.3V) (Video DAC 0)
131
VDAC_0
O
VDAC output 0
132
VDAC_DVSS
—
Ground terminal (Video DAC digital system)
133
VDAC_DVDD
—
Power supply terminal (+3.3V) (Video DAC digital system)
134
VDAC_REFVDD
—
Power supply terminal (Video DAC reference)
135
VDAC_REF
I
Reference voltage input terminal(for Video DAC)
136
VDAC_REFVSS
—
Ground terminal (Video DAC reference)
137
XVSS
—
Ground terminal (crystal oscillator)
138
XOUT
O
Crystal oscillation signal output
139
XIN
I
Crystal oscillation signal input
140
XVDD
—
Power supply terminal (crystal oscillator)
141
AVSS2
—
Ground terminal (analog PLL)
35
HCD-FR1/FR8/FR9
Pin No.
Pin Name
I/O
Description
142
AVDD2
—
Power supply terminal (+3.3V) (analog PLL)
143
AVDD1
—
Power supply terminal (+3.3V) (analog PLL)
144
AVSS1
—
Ground terminal (analog PLL)
145
VDD
—
Power supply terminal (+1.8V) (inside core)
146
GND
—
Ground terminal (inside core)
147
XCK
O
Audio system clock output (not used)
148
LRCK
O
LRCK signal output for audio (not used)
149
BCK
O
BCK signal output for audio (not used)
150
GPIO4 (1)
—
Not used (pull-up)
151
GPIO4 (2)
—
Not used (pull-up)
152
VDDP
—
Power supply terminal (+3.3V) (I/O signal)
153
GNDP
—
Ground terminal (I/O signal)
154
GPIO4 (3)
—
Not used (pull-down)
155
GPIO4 (4)
—
Not used (pull-down)
156
IEC958
O
S/PDIF signal
157
DAI_DATA
I
Data input from ADC (not used)
158
DAI_BCK
I
BCK signal input from ADC (not used)
159
DAI_LRCK
I
LRCK signal input from ADC (not used)
160
I2C_CL
I/O
I2C clock bus
161
I2C_DA
I/O
I2C data bus
162
CS(ZIVA_E2P)
O
Chip select signal output to the EEPROM (IC203)
163
RXD1
I
Serial data input for check jig
164
TXD1
O
Serial data output for check jig
165
WRITE_CTRL(ZIVA_E2P)
O
Write control signal output to the EEPROM (IC203)
166
GNDP
—
Ground terminal (I/O signal)
167
VDDP
—
Power supply terminal (+3.3V) (I/O signal)
168
SDDATA7
I
SDBus data7 input
169
SDDATA6
I
SDBus data6 input
170
SDDATA5
I
SDBus data5 input
171
SDDATA4
I
SDBus data4 input
172
GND
—
Ground terminal (inside core)
173
VDD
—
Power supply terminal (+1.8V) (inside core)
174
SDDATA3
I
SDBus data3 input
175
SDDATA2
I
SDBus data2 input
176
SDDATA1
I
SDBus data1 input
177
SDDATA0
I
SDBus data0 input
178
SDREQ
O
SDBus data request signal output
179
SDEN
I
SDBus data enable signal input
180
GNDP
—
Ground terminal (I/O signal)
181
VDDP
—
Power supply terminal (+3.3V) (I/O signal)
182
SDERROR
I
SDBus data error signal input
183
SDCLK
I
SDBus data clock input
184
HIRQ1
I
Interrupt signal input from the mechanism controller (IC301)
185
DRVCLK
I
Serial data clock input from the mechanism controller (IC301)
186
DRVTX
I
Serial data input from the mechanism controller (IC301) and the EEPROM (IC203)
187
DRVRX
O
Serial data output to the mechanism controller (IC301) and the EEPROM (IC203)
188
DRVRDY
I
Ready signal input from the mechanism controller (IC301)
36
HCD-FR1/FR8/FR9
Pin No.
Pin Name
I/O
Description
189
VNW
—
Power supply for 5V tolerance voltage input
190
ALE
O
Latch enable signal output for address data demux
191
RST_SPC
O
Reset signal output to the mechanism controller (IC301)
192
HCS3
O
Not used
193
HCS2
O
Chip select signal output for Medusa (not used)
194
HCS1
I/O
Not used
195
HCS0
O
Chip select signal output to the external ROM (IC205)
196
VDDP
—
Power supply terminal (+3.3V) (I/O signal)
197
TRST
I
Reset signal input
198
TDO
O
Data output
199
TDI
I
Data input
200
TMS
I
TMS signal input
201
TCK
I
TCK signal input
202
RESET
I
ZIVA reset input
203
BUS CLK
I/O
Not used
204
GND
—
Ground terminal (inside core)
205
VDD
—
Power supply terminal (+1.8V) (inside core)
206
HA3
I/O
Address bus 3
207
HA2
I/O
Address bus 2
208
GNDP
—
Ground terminal (I/O signal)
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