Sharp LC-M3700 (serv.man9) Service Manual ▷ View online
46
LC-M3700
LC-M3710
LC-M3710
46-1
46-2
Ë
9DK001-15103 (CXA3516R) (ASSY:IC10004)
3ch 8bit 165MSPS A/D Converter Amplifier PLL
»
Block Diagram
Pin No
.
Pin Name
I/O
Pin Function
1
B/CbOUT
O
B/Cb Amplifier output signal monitor
2
ADDRESS
I
I2C slave address setup
3
R/CrOUT
O
R/Cr Amplifier output signal monitor
4N
C
—
Not connected
5N
C
—
Not connected
6
XPOWERSAVE
I
Power save setup
7
DGNDREG
—
GND for registers
8
DVCCREG
—
Power supply for registers
9
SDA
I
Control register data input
10
SCL
I
Control register clock signal input
11
XSENABLE
I
Enable signal input for 3 line control registers
12
SEROUT
O
3
line control register data read-out
13
3WIRE
Å
^I2C
I
Selection in I2C-bus mode and 3 line bus mode
15
AVCCADREF
—
Power supply for reference voltage of ADC
16,94
AVCCAD3
—
Analog power supply of ADC
17
VRT
O
The top reference voltage output of ADC
18,92
DVCCAD3
—
Digital power supply of ADC
19,32,42,54,
DVCCADTTL
—
Power supply for a TTL output of ADC
65,76,90
20,33,44,55,
DGNDADTTL
—
GND for a TTL output of ADC
67,77,89
21,22,
RA0~RA7
O
R
channel port A side data output
24-28,31
»
Pin Function
Pin No
.
Pin Name
I/O
Pin Function
23,30,43,50,
DGNDAD3
—
Digital GND of ADC
59,66,79,86
29,80
AGNDAD3
—
Analog GND of ADC
34-41
RB0~RB7
O
R
channel port B side data output
45-49,51-53
BA0~BA7
O
B
channel port A side data output
56-58,60-64
BB0~BB7
O
B
channel port B side data output
68-75
GA0~GA7
O
G
channel port A side data output
78,81-85,87,88
GB0~GB7
O
G
channel port B side data output
91
DVCCAD
—
Digital power supply of ADC
93
VRB
O
Bottom reference voltage output of ADC
95
AGNDADREF
—
GND for reference voltage of ADC
96
DVCCPLLTTL
—
Power supply for a TTL output of PLL
97
DGNDPLLTTL
—
Power supply for a TTL output of PLL
98
XCLKCLK
O
C
LK reversal output
99
1/2XCLK
O
CLK output
100
1/2CLK
O
1/2 CLK reversal output
101
DSYNC/
O
1/2 CLK output
103
DIVOUT
O
DSYNC signal output/DIVOUT signal output
104
UNLOCK
O
UNLOCK signal output terminal
105
SOGOUT
O
Synchronization signal output of a sync-on green signal
106
HOLD
I
Input of de-servile signal of phase comparison
107
XTLOAD
I
Reset setup of a programmable counter
108
EVEN/ODD
I
Sampling clock reversal pulse input of ADC
109
XCLKIN
I
Negative clock input for a test
110
CLKIN
I
Positive clock input for a test
111
SYNCIN1
I
Synchronization signal input 1
112
SYNCIN2
I
Synchronization signal input 2
113
CLPIN
I
Clamp pulse input
114
DVCCPLL
—
Power supply for PLL
115
DGNDPLL
—
Digital ground for PLL
116
AVCCVCO
—
Analog power supply for VCO of PLL
117
AGNDVCO
—
Analog ground for VCO of PLL
118
RC1
—
PLL loop filter external terminal 1
119
RC2
—
PLL loop filter external terminal 2
120
AVCCIR
—
Analog power supply for IRFE
121
IREF
I
Current setup
123
AGNDIR
—
Analog ground for IRFE
124
G/YIN1
I
G/Y signal input 1
125
AVCCAMPG
—
Power supply for G/Y amplifier
126
G/YIN2
I
G/Y signal input 2
127
AGNDAMPG
—
Ground for G/Y amplifier
128
G/YCLP
—
Clamp capacitor connection terminal for G/Y brightness
129
B/CbCLP
—
Clamp capacitor connection terminal for B/Cb brightness
130
R/CrCLP
—
Clamp capacitor connection terminal for R/Cr brightness
132
SOGIN1
I
Sync-on green signal input 1
133
B/CbIN1
I
B/Cb signal input1
134
AVCCAMPB
—
Power supply for B/Cb amplifier parts
135
SOGIN2
I
Sync-on green signal input 2
136
B/CbIN2
I
B/Cb signal input 2
137
AGNDAMPB
—
Ground for B/Cb amplifier parts
139
R/CrIN1
I
R/Cr signal input 1
140
AVCCAMPR
—
Power supply for R/Cr amplifier parts
141
R/CrIN2
I
R/Cr signal input 2
142
AGNDAMPR
—
Ground for R/Cr amplifier parts
143
G/YOUT
O
Amplifier output signal monitor
144
DACTEST
O
For amplifier part control registers
Test output terminal of DAC
14,102,122,
OUTDPGND
—
Ground
131,138
47
LC-M3700
LC-M3710
LC-M3710
47-1
47-2
Ë
RH-iXA312WJN1Q(MT48LC2M32B2-512K) (ASSY:IC4702,4903)
64Mb: x32 SDRAM
»
Block Diagram
»
Pin Function
Pin No
.
P
in Name
I/O
Pin Function
68
CLK
I
C
lock: CLK is driven by the system clock. All SDRAM input signals are sampled
on the positive edge of CLK. CLK also increments the internal burst counter and
controls the output registers.
67
CKE
I
C
lock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides PRECHARGE POWER-DOWN and SELF
REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in
any bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is
synchronous except after the device enters power-down and self refresh
modes, where CKE becomes asynchronous until after exiting the same mode.
The input buffers, including CLK, are disabled during power-down and self
refresh modes, providing low standby power. CKE may be tied HIGH.
20
CS#
I
Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH.
CS#provides for external bank selection on systems with multiple banks.
CS# is considered part of the command code.
17, 18, 19
WE#, CAS#,RAS#
I
Command Inputs: WE# , CAS#, and RAS# (along with CS#) define the
command being entered.
16, 71, 28, 59
DQM0-DQM3
I
Input/Output Mask: DQM is sampled HIGH and is an input mask signal for write
accesses and an output enable signal for read accesses. Input data is masked
during a WRITE cycle. The output buffers are placed in a High-Z state (two-
clock latency) during a READ cycle. DQM0 corresponds to DQ0-DQ7; DQM1
corresponds to DQ8-DQ15; DQM2 corresponds to DQ16-DQ23; and DQM3
corresponds to DQ24-DQ31. DQM0-DQM3 are considered same state when
referenced as DQM.
22, 23
BA0, BA1
I
Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ,
WRITE or PRECHARGE command is being applied.
25-27, 60-66, 24
A0-A10.
I
Address Inputs: A0-A10 are sampled during the ACTIVE command (rowaddress
A0-A10) and READ/WRITE command (column-address A0-A7 with A10
defining auto precharge) to select one location out of the memory array in the
respective bank. A10 is sampled during a PRECHARGE command to determine
if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1
(LOW). The address inputs also provide the op-code during a LOAD MODE
REGISTER command.
2, 4, 5, 7, 8, 10,
DQ0-DQ31
I/O
Data I/O: Data bus.
11, 13,
74, 76, 77, 79,
80, 82, 83,
85, 31, 33, 34,
36, 37, 39,
40, 42, 45, 47,
48, 50, 51,
53, 54, 56
14, 21, 30, 57,
NC
—
No Connect: These pins should be left unconnected.
69,70, 73
3, 9, 35, 41, 49,
N.C.
—
DQ Power Supply: Isolated on the die for improved noise immunity.
55, 75, 81
6, 12, 32, 38,
VR4
O
DQ Ground: Provide isolated ground to DQs for improved noise immunity.
46, 52, 78, 84
1, 15, 29, 43
VR3
O
Power Supply: +3.3V ±0.3V.
44, 58, 72, 86
N.C.
—
Ground.
48
LC-M3700
LC-M3710
LC-M3710
48-1
48-2
Ë
RH-iXA350WJZZQ(IR3E11M1) (ASSY:IC4105)
IC for TFT-LCD of gradation reference voltage.
»
Block Diagram
Pin No
.
Pin Name
I/O
Pin Function
»
Pin Function
1
VL1
O
L1 amplifier output
2
VL2
O
L2 amplifier output
3
N.C.
—
Non-connected terminal
4
VL3
O
L3 amplifier output.
5
VL4
O
L4 amplifier output.
6
N.C.
—
Non-connected terminal
7
N.C.
—
Non-connected terminal
8
N.C.
—
Non-connected terminal
9
VCC2
—
Power supply terminal.
10
N.C.
—
Non-connected terminal.
11
VR4
O
R3 amplifier output.
12
VR3
O
R4 amplifier output.
13
N.C.
—
Non-connected terminal
14
VR2
O
R2 amplifier output.
15
VR1
O
R1 amplifier output.
16
N.C.
—
Non-connected terminal
17
VR0
O
R0 amplifier output.
18
VCC1
—
Power supply terminal.
19
VR
I
REF amplifier reference input terminal.
20
VREF
O
R
EF amplifier output.
21
N.C.
—
Non-connected terminal
22
VA0
I
R0 amplifier reference input terminal.
23
VA1
I
R1 amplifier reference input terminal.
24
N.C.
—
Non-connected terminal
25
VA2
I
R2 amplifier reference input terminal.
26
VA3
I
R3 amplifier reference input terminal.
27
N.C.
—
Non-connected terminal
28
VA4
I
R4 amplifier reference input terminal.
29
GND2
—
Ground terminal.(for OP amplifier)
30
N.C.
—
Non-connected terminal
31
N.C.
—
Non-connected terminal.
32
N.C.
—
Non-connected terminal.
33
VB4
I
L4 amplifier reference input terminal.
34
N.C.
—
Non-connected terminal.
35
VB3
I
L3 amplifier reference input terminal.
36
VB2
I
L2 amplifier reference input terminal.
37
N.C.
—
Non-connected terminal.
38
VB1
I
L1 amplifier reference input terminal.
39
VB0
I
L0 amplifier reference input terminal.
40
N.C.
—
Non-connected terminal.
41
GND1
—
Ground terminal.
42
COMI
I
COM amplifier reference input terminal.
43
COMO
O
COM amplifier output.
44
COMS
I
COM amplifier reversal input terminal
45
N.C.
—
Non-connected terminal.
46
N.C.
—
Non-connected terminal.
47
VLO
O
L
0 amplifier output.
48
N.C.
—
Non-connected terminal.
49
LC-M3700
LC-M3710
LC-M3710
49-1
49-2
Ë
VHiMB8346BV-1Y(ASSY:IC2006)
D/A CONVERTOR
»
Block Diagram
Pin No
.
Pin Name
I/O
Pin Function
17
DI
I
Data input terminal.
12-bit serial data is inputted.
14
DO
O
D
ata output terminal.
Bit data of MSB of a 12-bit shift register is outputted.
16
CLK
I
Shift clock input terminal.
Incoming signal from DI terminal is inputted into a 12-bit shift register in the
leading edge of a shift clock.
15
LD
I
Load signal input terminal.
An input of the "H" level loads the data of a 12-bit shift register to a decoder and
the register for an D/A output.
18
AO1
O
D/A output terminal.
19
AO2
O
Analog data of a 8-bit D/A converter with an OP amplifier is outputted.
2
AO3
O
3
AO4
O
4
AO5
O
5
AO6
O
6
AO7
O
7
AO8
O
8
AO9
O
9
AO10
O
12
AO11
O
13
AO12
O
11
Vcc
—
MCU interface and the power supply terminal of an OP amplifier.
20
GND
—
MCU interface and the ground terminal of an OP amplifier.
10
Vdd
—
Power supply terminal for D/A converter.
1
Vss
—
Ground terminal for D/A converter.
»
Pin Function
»
Pin Function
Ë
VHiMD1422N+-1Y(ASSY:IC1703)
DC-DC converter power IC
»
Block Diagram
Pin No
.
Pin Name
I/O
Pin Function
1
S/S
I
capacitor connection terminal for a soft start.
2
OCL-
I
Over(-) current-detection terminal.
3
OCL+
I
Over-current (+) detection terminal.
4,26
GND
—
GND terminal.
5
R/C
I
R
emote ON/OFF control terminal.
6
Vcc
—
Power supply terminal of a control circuit.
8
Vboot
I
Power supply terminal of a main switch and MOSFET control circuit.
9
VGL
I
Gate terminal of the Low side MOSFET for periodic rectification.
11~14
VOUT
O
Output terminal of the power stage.
16
P.GND
—
GND terminal of an output circuit.
18~21
VDD
—
Power supply terminal of the main switch MOSFET.
23
VGH
I
Gate terminal of the high side MOSFET for periodic rectification.
25
VB
I
Output bootstrap terminal.
Capacitor is connected between VB terminal and VOUT and the circuit for
control of MOSFET inside IC is bootstrapped.
27
VTS
—
Terminal for TEST. Please do not connect anywhere.
28
Vref
I
Internal standard voltage output terminal.
30
ampOUT
O
B
uilt-in error amplifier output terminal.
32
amp-
I
Built-in error amplifier reversal input terminal. .
7,10,15,17,
N/C
—
It is a no-connection terminal.
22,24,29,31
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