Sharp LC-M3700 (serv.man9) Service Manual ▷ View online
38
LC-M3700
LC-M3710
LC-M3710
38-1
38-2
Ë
VHiTB1274AF1QE(ASSY:IC801)
VIDEO/CHROMA/SYNC Processor
»
Block Diagram
»
Pin Function
Pin No
.
Pin Name
I/O
Pin Function
1
CVBS1/Y1-IN
I
CVBS1 or a Y1-IN signal is inputted.
2
SYNC-IN
I
Synchronized signal is inputted.
3
CVBS-OUT
O
Output terminal of CVBS or a Y+C signal.
4
V
S
O
Counted-down vertical synchronized signal is outputted.
5
COMB Y-IN
I
Y-signal outputted from comb-filter is inputted.It opens, when not using it.
6
D-VDD
—
Power supply of a DDS/BUS/V-CD/H-CD block is supplied.DC5V (standard)
7
COMB C-IN
I
C-signal outputted from comb-filter is inputted.It opens, when not using it.
8
D-GND
—
GND terminal of a DDS/BUS/V-CD/H-CD block.
9
H
S
O
Horizontal synchronized signal which required H-AFC is outputted.
10
SCP
O
Sand Castle Pulse is outputted. A clamp pulse and a horizontal Blanking pulse
are outputted.
11
Yvi-IN
O
Y-signal for a synchronous input selected by Video-SW is outputted.
12
SYNC-VCC
—
Power supply of a SYNC/HVCO block is supplied.DC5V (standard)
13
SCL
I
SCL terminal of I2CBUS.
14
SDA
I/O
SDA terminal of I2CBUS.
15
YS3
I
Selecte SW of a main signal and RGB1 input signal.
(RGB1-in)
Only when [RGB1-ENB] is set as "enable" by bus setup, the input of YS3
becomes effective.
16
SYNC-GND
—
GND terminal of a SYNC/HVCO block.
17
Cr1-IN
I
Y1-/Cb1/Cr1 signal is inputted.
18
Cb1-IN
I
19
Y1-IN
I
20
CLP-FIL
—
Filter for Y clamp is connected.
21
Y-OUT
O
Y/Cb/Cr signal is outputted.
22
Cb-OUT
O
23
Cr-OUT
O
24
YS1
I
Selecte SW of a main signal and YCrCb2 input signal.
(YVbC2-IN)
25
B1-IN
I
RGB1 signal is inputted. This input is selected in YS3 or I2CBUS.
26
G1-IN
I
27
R1-IN
I
28
Y/C-GND
—
GND terminal of Y/C/Text/Video-SW / 1HDL block.
29
Cr2-IN
I
Y2/Cb2/Cr2 signal is inputted. This input is selected in YS1.
30
Cb2-IN
I
It opens, when not using it.
31
Y2-IN
I
32
Y/C-VCC
—
Power supply of Y/C/Text/Video-SW / 1HDL block is supplied.DC5V (standard)
33
B2-IN
I
RGB2 signal is inputted. This input is selected in YS2.
It opens, when not using it.
34
G2-IN
I
35
R2-IN
I
36
YS2/YM
I
Selecte SW of a main signal and RGB2 input signal.
(RGB2-IN)
37
FIL.
—
Connects with a Y/C-VCC terminal.
38
X'TAL
—
16.2MHz X'tal oscillation element is connected.
39
C3-IN
I
Chrominance signal is inputted. It opens, when not using it.
40
APC-FIL
—
Filter for a chrominance demodulater is connected.
41
CVBS3/Y3-IN
I
CVBS3 or Y3 signal is inputted. It opens, when not using it.
42
ADDRESS
I
Slave address is set up.
43
C2-IN
I
Chrominance signal is inputted. It opens, when not using it.
44
CVBS2/Y2-IN
I
CVBS2 or Y2 signal is inputted. It opens, when not using it.
45
COMB SYS
O
The distinction result of the received color system is outputted from this terminal
and a terminal 46.
46
Fsc-OUT
O
Subcarrier is outputted.
47
AFC-FIL
—
Filter for AFC detection is connected.
48
C1-IN
I
Chrominance signal is inputted. It opens, when not using it.
39
LC-M3700
LC-M3710
LC-M3710
39-1
39-2
Ë
VHiPD64084+-1Q(ASSY:IC7001)
3-Dimensiona Y/C Separation LSI with a built-in 4M bit Memory
»
Block Diagram
»
Pin Function
Pin No
.
Pin Name
I/O
Pin Function
1,33,48,75
DGND
—
Digital part GND (common to I/O part grounding)
39,62,100
DVDD
—
Digital part 2.5V power supply
4-12,28-30,
TEST01-
Test terminal (OPEN or GND connection)
32,40-43,
TEST26
78-85,99
13
EXTALTF
O
Extended 4fsc and an alternat-flag output terminal
14-23
EXTDYCO0-
I/O
Extended digital input-and-output terminal
EXTDYCO9
24-25
DGNDRAM
—
DRAM part GND
26-27
DVDDRAM
—
DRAM part 2.5V power supply
31
DVDDIO
—
I/O part 3.3V power supply
34-35
AGND
—
OSC circuit part GND
36
XI
I
Standard clock input
37
XO
O
Standard clock reversal output
38
AVDD
—
OSC circuit part 2.5V power supply
44
RPLL
I
Test input terminal (GND connection)
45
SLA0
I
I2C-bus slave address selection input
46
SCL
I
I2C-bus clock input
47
SDA
I/O
I2C-bus clock output
49
AGND
—
I2C-bus data input-and-output terminal
50
AVDD
—
fsc DAC section 2.5V power supply
51
FSCO
O
fsc generator fsc output
52-53
AGND
—
8fsc PLL section grounding
54
FSCI
I
8fsc PLL fsc input
55
AVDD
—
8fsc PLL section 2.5V power supply
56
CKMD
I
CLK8 test mode selection (GND connection)
57
CLK8
I/O
CKMD = 0 : 8fSC clock output
CKMD = 1 : 8fsc clock input
58
RSTB
I
System reset input (active low)
59
ST0
O
Internal signal monitor output
60
ST1
O
Internal signal monitor output
61
NSTD
O
Non-standard detection monitor output
(L : A standard judging , H : Non-standard judging)
63-72
DYCO0-DYCO9
I/O
Digital input and output
73
ALTF
O
4fsc alternat-flag output
74
LINE
I
Compulsive line processing selection input
(L : It is usually Processing H. : Processing between compulsive lines)
76
KIL
I
External killer input
(L : It is usually Processing H. : Compulsive Y/C separation stop)
77
CSI
I
Composite sync. input (active low)
2
TESTIC1
I
T
he test terminal for IC sorting (GND connection)
3
TESTIC2
I
The test terminal for IC sorting (GND connection)
86
AVDD
—
Y-DAC and C-DAC part 2.5V power supply
87
CBPC
O
C-DAC phase compensation output
88
ACO
O
C-DAC analog C-signal output
89
AYO
O
C-DAC analog Y-signal output
90
CBPY
O
Y-DAC phase compensation output
91
AGND
—
Y-DAC and C-DAC part grounding
92
AGND
—
ADC section grounding
93
AYI
I
ADC analog composite signal input
94
VCLY
O
ADC clamp potential output
95
VRBY
O
ADC bottom standard voltage output
96
VRTY
O
ADC top standard voltage output
97
VCOMY
O
ADC standard voltage of the same phase
98
AVDD
—
ADC section 2.5V power supply
40
LC-M3700
LC-M3710
LC-M3710
40-1
40-2
Pin No
.
Pin Name
I/O
Pin Function
1
G
ND_OUT
O
GND terminal only for RGB_OUT output stages.
2
YSYM2
I
Control input terminal of YS2/YM2.
VM is turned off if an input level reaches the level of YM.
3
GND_SIG
—
GND terminal of Y-component and a RGB system.
4
B2_IN
I
Signal input terminal of an analog RGB 2.
5
G2_IN
I
6
R2_IN
I
7
YSYM1
I
Control input terminal of YS1/YM1.
VM is turned off if an input level reaches the level of YM.
8
B1_IN
I
Signal input terminal of an analog RGB 1.
9
G1_IN
I
10
R1_IN
I
11
PABL_FIL
Peak hold terminal of Peak ABL.
12
DPDT_OFF
I
Terminal which carries out signal section detection of dynamic picture (black
extension) operation and the rate of direct-current transmission to un-operating .
13
YF_OFF
I
Terminal for turning off VM, sharpness, and colour.
An input level corresponds with three values.
Ë
VHiCXA2150Q-1Q(ASSY:IC8802)
RGB processor
»
Block Diagram
»
Pin Function
Pin No
.
Pin Name
I/O
Pin Function
14
VM_OUT
O
VM output terminal.
The differentiation waveform of Y signal is outputted by positive.
15
VM_MOD
I
Terminal which modulates VM level.It becomes an output 0 less than 1.5V.
It becomes modulation by 1.5-3.5V.It becomes demodulation more than by 3.5V.
16
CLP_C
Connection terminal of the capacitor for Y-system clamp.
17
BPH
A capacitor is connected to black detection of dynamic picture(black extension) at GND.
18
IREF_YC
Terminal for reference current creation of Y-component signal processing system.
19
Vcc5
—
Power supply terminal of Y-component system, a RGB system, and the I2C
BUS section.
20
Y_IN
I
Signal input terminal of external YCbCr.
21
CB_IN
I
22
CR_IN
I
23
F0
I
F
ree run frequency setting terminal.
24
F1
I
25
SDA
I/O
SDA (Serial Data) input terminal of a I2C BUS standard.
26
SCL
I
SCL
Å
iSerial Clock
Å
j input terminal of a I2C BUS standard.
27
SCP
O
S
and castle pulses output terminal.
H of Abbreviation 0-2.5V and a VBLK pulse are overlapped on the clamp pulse
of Abbreviation 0-5V, and it is outputted to them.
28
HS_IN
I
HSYNC input terminal. It inputs by the phase of a sync.
29
VREG5
Shant regulator of 5V is formed by connecting NPN-Tr for feedback to 30pin
30
VBIAS
VBIAS and 29pin VREG5 by external.
31
IREF_HV
H-system and V-system terminal for reference current creation.
32
AFC_FIL
AFC lug-lead filter terminal.
33
CERA
Terminal for 2.7MHz ceramic oscillation segment connection.
34
HPROT
I
Input terminal of the hold down signal of HD output.
If this terminal is carried out more than 2V more than 7V cycles, a hold down function will
work, HD output is held by Hi-Z, and it acts as all the Blanc kings of the RGB output.
35
VPROT
I
V-protection input terminal.
When a protection function works, a RGB output serves as all the blankings,
and "1" is outputted to a status register "VNG."
36
HCOMP_IN
I
Voltage input terminal for high-pressure change compensation.
The high-pressure compensation about DC amplitude of an EW_DRV signal
and the phase of a H_DRV signal is performed.
37
VCOMP_IN
I
Voltage input terminal for high-pressure change compensation.
The high-pressure compensation about the amplitude of a V_DRV signal is performed.
38
L2_FIL
Filter terminal for 2nd loops of AFC.
39
HP_IN
I
Input terminal of H deviation pulse for H-AFC.
40
H_DRV
O
Output terminal of H-drive signal.
41
GND_H
—
GND terminal of a horizontal deviation (H) system.
42
VS_IN
I
VSYNC input terminal.
43
HC_PARA
O
Wide use V-parabola wave output terminal.
44
GND_V
—
GND terminal of a vertical deviation (V) system.
45
MP_PARA
O
Wide use V-parabola wave output terminal.
46
DF_PARA
O
47
EW_DRV
O
V-parabola wave output terminal.
It is used for compensation of horizontal amplitude and horizontal pin distortion.
48
V_OSC
Terminal for saw tooth wave creation.
49
V_AGC
Sample hold terminal for AGC which makes amplitude of V-saw tooth wave regularity.
50
VSAW0
O
Output terminal of V-saw tooth wave (VSAW0).
51
VSAW1
O
Output terminal of V-saw tooth wave (VSAW1).
52
V_DRV-
O
Output terminal of V-saw tooth wave.
53
V_DRV+
O
V_DRV- and V saw tooth wave output terminal of reverse polarity.
54
VTIM
O
V-timing pulse output terminal.It is the plus terminal positive pulse of 0-5V.
The High period is in agreement with the position of VBLK of a RGB output.
55
Vcc9
—
Power supply terminal of a vertical deviation (V) system.
56
ABL_IN
I
Terminal of the control signal input of ABL.It operates as an average value type.
57
ABL_FIL
Capacitor is connected in order to form LPF to an ABL_IN incoming signal.
58
IK_IN
I
A
reference pulse is returned to this terminal.
59
SABL_IN
I
Signal input terminal for SABL compensation.
60
PRE_RGB
O
Object for high-pressure drawing bend compensation, and a signal output
terminal for SABL compensation.
The signal which MIX(ed) the RGB signal is outputted.
61
VCC_OUT
—
Power supply terminal for RGB output stages.
62
B_OUT
O
RGB signal output terminal.Signal of 2.6 Vp-p is outputted by 100IRE.
63
G_OUT
O
64
R_OUT
O
»
Pin Function
41
LC-M3700
LC-M3710
LC-M3710
41-1
41-2
Ë
VHiSM5301AS-1Y(ASSY:IC8805)
3ch output video buffer with a built-in high band filter.
»
Block Diagram
1
GINA/UINA
I
Analog GINA or a UINA signal input terminal. A synchronized signal is inputted
from a SYNCIN terminal.
2
GSG1
I
The terminal for a GOUT/UOUT output buffer gain setup.
3
GINB/UINB
I
Analog GINB or a UINB signal input terminal. A synchronized signal is inputted
from a SYNCIN terminal.
4N
C
—
Not connected
5
BINA/VINA
I
Analog BINA or a VINA signal input terminal. A synchronized signal is inputted
from a SYNCIN terminal.
6
GSB1
I
The terminal for a BOUT/VOUT output buffer gain setup.
7
BINB/VINB
I
Analog BINB or a VINB signal input terminal. A synchronized signal is inputted
from a SYNCIN terminal.
8N
C
—
Not connected
9
DISABLE
I
Power save function. Pull down resistance built-in.
L : Enable
H : Disable(output terminal : ROUT/YOUT, GOUT/UOUT and BOUT/VOUT are
high impedance.)
10
GND3
—
Analog GND terminal.
11
BOUT/VOUT
O
B/V signal output terminal
12
VCC3
—
Analog 5V power supply terminal.
13
GND2
—
Analog GND terminal.
14
GOUT/UOUT
O
G/U signal output terminal
15
VCC2
—
Analog 5V power supply terminal.
16
GND1
—
Analog GND terminal.
17
ROUT/YOUT
O
R/Y signal output terminal
18
VCC1
—
Analog 5V power supply terminal.
19
GND4
—
Analog GND terminal.
20
RFC
I
L.P.F.(Low path filter) The resistance connection terminal for a cutoff frequency setup.
21
VFC
I
L.P.F.(Low path filter) The resistance connection terminal for a cutoff frequency setup.
22
MUXSEL
I
Input terminal selection signal. Pull down resistance built-in.
L : XINA terminal side is chosen.
H : YINB terminal side is chosen.
23
SYNCIN
I
The external H-sync signal input terminal for filter channels.
Active "H." Pull down resistance built-in.
24
VCC4
—
Analog 5V power supply terminal.
25
RINA/YINA
I
Analog RINA or a YINA signal input terminal. A synchronized signal is inputted from a SYNCIN terminal.
26
GSR1
I
The terminal for a ROUT/YOUT output buffer gain setup.
27
RINB/YINB
I
Analog RINB or a YINB signal input terminal. A synchronized signal is inputted from a SYNCIN terminal.
28
NC
—
Not connected
Pin No
.
Pin Name
I/O
Pin Function
»
Pin Function
Ë
VHiTC90A69F-1Y(ASSY:IC401)
3 Line Digital Comb Filter
»
Block Diagram
Pin No
.
Pin Name
I/O
Pin Function
»
Pin Function
1
BIAS
—
Bias for ADC
2
VRT
—
D range upper bias for ADC
3
VDD1
—
Power supply for ADC and DAC (analog system)
4
TESTI1
I
Test input
5
VSS2
—
GND for ADC (analog system)
6
VRB
—
D range lower bias for ADC
7
YCIN
I
Picture signal input
8
TEST
O
Reset control and TEST control at the time of shipment
9
KILLER
I
Y/C separation and vertical enhancer-off control
10
TESTI2
I
Test input
11
VDD3
—
Power supply for logic (digital system)
12
VSS3
—
GND for Logic and DRAM (digital system)
13
VDD2
—
Power supply for DRAM (digital system)
14
TESTI3
I
Test input
15
SCL
I
Clock input of IIC BUS
16
SDA
I
Data input of IIC BUS
17
MODE1
O
MODE1 output
18
TESTOUT
I
Test input
19
FSC
I
Clock input
20
VDD4
—
Power supply for PLL (analog system)
21
VSS4
—
GND for PLL (analog system)
22
FIL
I
VCO control
23
PD
O
P
LL detection output
24
VB2
—
Bias 2 for DAC
25
YOUT
O
Luminosity signal output
26
VSS1
—
GND for DAC (analog system)
27
COUT
O
Color signal output
28
VB1
—
Bias 1 for DAC
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