Sharp LC-M3700 (serv.man9) Service Manual ▷ View online
42
LC-M3700
LC-M3710
LC-M3710
42-1
42-2
Ë
RH-iX3370CEN1,MSP3440G(ASSY:IC2501)
SOUND PROCCESSOR
»
Block Diagram
»
Pin Function
Pin No
.
Pin Name
I/O
Pin Function
1N
C
—
Not connected
2
I2C_CL
I/O
I2C clock
3
I2C_DA
I/O
I2C data
4
I2S_CL
I/O
I2S clock
5
I2S_WS
I/O
I2S word strobe
6
I2S_DA_OUT
O
I2S data output
7
I2S_DA_IN1
I
I2S1 data input
8
ADR_DA
O
ADR data output
9
ADR_WS
O
A
DR word strobe
10
ADR_CL
O
ADR clock
11,12,1
DVSUP
—
Digital power supply 5V
14,15,16
DVSS
—
Digital ground
17
I2S_DA_IN2
I
I2S2-data input
18,19,20
NC
—
Not connected
21
RESETQ
I
Power-on-reset
22,23
NC
—
Not connected
24
DACA_R
O
Headphone out, right
25
DACA_L
O
Headphone out, left
26
VREF2
—
Reference ground 2
27
DACM_R
O
L
oudspeaker out, right
28
DACM_L
O
Loudspeaker out, left
29
NC
—
Not connected
30
DACM_SUB
O
Subwoofer output
31,32
NC
—
Not connected
33
SC2_OUT_R
O
SCART 2 output, right
34
SC2_OUT_L
O
SCART 2 output, left
35
VREF1
—
Reference ground 1
36
SC1_OUT_R
O
SCART 1 output, right
37
SC1_OUT_L
O
SCART 1 output, left
38
CAPL_A
—
Volume capacitor AUX
39
AHVSUP
—
Analog power supply 8V
40
CAPL_M
—
Volume capacitor MAIN
41,42
NC
—
Not connected
43,44
AHVSS
—
Analog ground
45
AGNDC
—
Analog reference voltage
46
NC
—
Not connected
47
SC4_IN_L
I
S
CART 4 input, left
48
SC4_IN_R
I
SCART 4 input, right
49
ASG4
—
Analog Shield Ground 4
50
SC3_IN_L
I
SCART 3 input, left
51
SC3_IN_R
I
SCART 3 input, right
52
ASG2
—
Analog Shield Ground 2
53
SC2_IN_L
I
SCART 2 input, left
54
SC2_IN_R
I
SCART 2 input, right
55
ASG1
—
Analog Shield Ground 1
56
SC1_IN_L
I
SCART 1 input, left
57
SC1_IN_R
I
SCART 1 input, right
58
VREFTOP
—
Reference voltage IF A/D converter
59
NC
—
Not connected
60
MONO_IN
I
Mono input
61,62
AVSS
—
Analog ground
63,64
NC
—
Not connected
65,66
AVSUP
—
Analog power supply 5V
67
ANA_IN1+
I
IF input 1
68
ANA_IN-
I
IF common (can be left vacant, only if IF input 1 is also not in use)
69
ANA_IN2+
I
IF input 2 (can be left vacant, only if IF input 1 is also not in use)
70
TESTEN
I
Test pin
71
XTAL_IN
I
Crystal oscillator
72
XTAL_OUT
O
73
TP
—
Test pin
74
AUD_CL_OUT
O
Audio clock output(18.432MHz)
75,76
NC
—
Not connected
77
D_CTR_I/O_1
I/O
D_CTR_I/O_1
78
D_CTR_I/O_0
I/O
D_CTR_I/O_0
79
ADR_SEL
I
I2C Bus address select
80
STANDBYQ
I
Stand-by(low-active)
43
LC-M3700
LC-M3710
LC-M3710
43-1
43-2
Ë
VHiNJU26150-1Q(ASSY:IC2510)
DIGITAL AUDIO PROCESSOR
»
Block Diagram
»
Pin Function
Pin No
.
Pin Name
I/O
Pin Function
1
SDO2
O
Sound data output CH2
2
SDO1
O
Sound data output CH1
3
SDO0
O
Sound data output CH0
4
SDA2
I/O
I2C I/O (for download)
5
SCL/SCK
I
I2C clock / serial clock
6
SDA/SDOUT
I/O
I2C I/O / serial out
7
AD1/SDIN
I
I2C address / serial in
8
AD2/SSX
I
I2C address / serial enable
9
VDDO
—
Power supply for oscillator (+2.5V)
10
XI
I
Clock input terminal
11
XO
O
Output for VCO connection
12
VSSO
—
Oscillator power supply GND
13
RESET
I
Reset terminal
14
VDDC
—
Internal power supply +2.5V
15
VSSC
—
Internal power supply GND
16
SCL2
I/O
I2C clock output (for download)
17
VDDC
—
Internal power supply +2.5V
18
VDDC
—
Internal power supply +2.5V
19
VSSC
—
Internal power supply GND
20
VSSC
—
Internal power supply GND
21
VDDR
—
Power supply for I/O (+2.5V)
22
VDDR
—
Power supply for I/O (+2.5V)
23
VSSR
—
I/O ground
24
VSSR
—
I/O ground
25
SDI0
I
Sound data output channel 0
26
SDI1
I
S
ound data output channel 1
27
SDI2
I
S
ound data output channel 2
28
LRI
I
LR clock input
29
BCKI
I
Bit clock input
30
MCK
O
A/D, D/A clock input
31
BCKO
O
Bit clock output
32
LRO
O
LR clock output
Ë
VHiTA2024++-1Y (ASSY:IC2303)
STEREO 15W (4
Ω
) DIGITAL AUDIO AMPLIFIER
»
Block Diagram
Pin No
.
Pin Name
I/O
Pin Function
»
Pin Function
2,3
DCAP2,
Charge pump switching pins. DCAP1 (pin 3) is a free running 300kHz square
DCAP1
wave between VDDA and DGND (12Vpp nominal). DCAP2 (pin 2) is level shifted
10 volts above DCAP1 (pin 3) with the same amplitude (12Vpp nominal),
frequency, and phase as DCAP1.
4,9
V5D, V5A
—
Digital 5VDC, Analog 5VDC
5,8,17
AGND1,
—
Analog Ground
AGND2,
AGND3
6
REF
—
Internal reference voltage; approximately 1.0 VDC.
7
OVERLOADB
A logic low output indicates the input signal has overloaded the mplifier.
10,14
OAOUT1,
O
Input stage output pins.
OAOUT2
11,15
INV1,
Single-ended inputs. Inputs are a "virtual" ground of an inverting opamp with
INV2
approximately 2.4VDC bias.
12
MUTE
When set to logic high, both amplifiers are muted and in idle mode. When low
(grounded), both amplifiers are fully operational. If left floating, the device stays
in the mute mode. This pin should be tied to GND if not used.
16
BIASCAP
Input stage bias voltage (approximately 2.4VDC).
18
SLEEP
When set to logic high, device goes into low power mode. If not used, this pin
should be grounded
19
FAULT
A logic high output indicates thermal overload, or an output is shorted to ground,
or another output.
20,35
PGND2,
—
Power Grounds (high current)
PGND1
22
DGND
—
Digital Ground. Connect to AGND locally (near the TA2024).
24,27,
OUTP2 & OUTM2,
O
Bridged output pairs
31,28
OUTP1 & OUTM1
25,26,
VDD2,VDD2,
Supply pins for high current H-bridges, nominally 12VDC.
29,30
VDD1,VDD1
13,21,23,
N
C
—
Not connected. Not bonded internally.
32,34
33
VDDA
—
Analog 12VDC
36
CPUMP
Charge pump output (nominally 10V above VDDA)
1
5VGEN
Regulated 5VDC source used to supply power to the input section (pins 4 and 9).
44
LC-M3700
LC-M3710
LC-M3710
44-1
44-2
Ë
VHiFA3675F/-1 (ASSY:IC1704)
6-channel DC-DC converter IC
»
Block Diagram
»
Pin Function
Pin No
.
P
in Name
I/O
P
in Function
1
VCC1
—
Power supply for control circuit.
2R
T
—
Oscillator timing resistor.
3C
T
—
Oscillator timing capacitor.
4
CS3
—
Soft start for Ch.3 & Ch.4.
5
CS5
—
Soft start for Ch.6.
6
CS4
—
Soft start for Ch.5.
7
CS1
—
Soft start for Ch.1
8
CS2
—
Soft start for Ch.2.
9
VREF
O
Reference voltage output.
10
CREF
O
Capacitor for reference voltage output.
11
VREG
O
Regulated for voltage output.
12
IN2-
I
Ch.2 inverting input to error amplifier.
13
FB2
O
C
h.2 output of error amplifier.
14
IN1-
I
Ch.1 inverting input to error amplifier.
15
FB1
O
C
h.1 output of error amplifier.
16
IN5+
I
Ch.5 non-inverting input to error amplifier.
17
IN5-
I
Ch.5 inverting input to error amplifier.
18
FB5
O
C
h.5 output of error amplifier.
19
IN6-
I
Ch.6 inverting input to error amplifier.
20
FB6
O
Ch.6 output of error amplifier.
21
IN3+
I
Ch.3 non-inverting input to error amplifier.
22
IN3-
I
Ch.3 inverting input to error amplifier.
23
FB3
O
C
h.3 output of error amplifier.
24
IN4+
I
Ch.4 non-inverting input to error amplifier.
25
IN4-
I
Ch.4 inverting input to error amplifier.
26
FB4
O
Ch.4 output of error amplifier.
27
CP
I
Timing capacitor for timer latch delay.
28
GND
—
Ground.
29
TLSEL
I
Ch.3 & Ch.4 timer latch selection(Low:disable).
30
CNT5
I
Ch.6 ON/OFF function.
31
CNT4
I
Ch.5 ON/OFF function.
32
CNT2
I
Ch.2 ON/OFF function.
33
CNT3
I
C
h.3 & Ch.4 ON/OFF function.
34
CNT1
I
Ch.1 ON/OFF function.
35
VCC2
—
Power supply for output stage.
36
VDRV
O
B
ias for logic circuit of output.
37
PGND1
—
Power ground.
38
OUT1S
O
Ch.1 source electrode of output stage.
39
OUT1
O
Ch.1 output(for Pch-MOSFET)
40
OUT4
O
Ch.4 output(for Pch-MOSFET)
41
OUT3
O
Ch.3 output(for Pch-MOSFET)
42
OUT2S
O
Ch.2 source electrode of output stage.
43
OUT2
O
Ch.2 output(for Pch-MOSFET)
44
OUT6S
O
Ch.6 source electrode of output stage.
45
OUT6
O
Ch.6 output(for Pch-MOSFET)
46
OUT5
O
Ch.5 output(for Pch-MOSFET)
47
OUT5S
O
Ch.5 source electrode of output stage.
48
PGND2
—
Power ground.
45
LC-M3700
LC-M3710
LC-M3710
45-1
45-2
Ë
RH-iX3270CEZZ (ASSY:IC10001)
IC32bit RISC Micro Processor
»
Pin Function
Pin No
.
Pin Name
I/O
Pin Function
34,36-44,
D[15:0]
I/O
Data bus D[15:0]
46,48-52
23-26,28,30-32
D[23:16/PTA[7:0]
I/O
Data bus D[23:16]/I/O port A[7:0]
13-18,20,22
D[31:24/PTB[7:0]
I/O
Data bus D[31:24]/I/O port B[7:0]
86,84,82,78-72,
A[25:0]
O
Address bus A[15:0]
70-68-60,56-53
96
CS0
O
Chip select 0
98
CS2/PTK[0]
O/(I/O)
Chip select 2/I/O port K[0]
99
CS3/PTK[1]
O/(I/O)
Chip select 3/I/O port K[1]
100
CS4/PTK[2]
O/(I/O)
Chip select 4/I/O port K[2]
101
CS5/CE1E/PTK[3]
O/(I/O)
Chip select 5/CE1(area 5SPCMIA)/O port K[3]
102
CS6/CE1B
0
Chip select 6/CE1(area 6SPCMIA)
87
BS/PTK[4]
O/(I/O)
Bus cycle startup signal /I/O port K[4]
118
RAS3U/PTE[2]
O/(I/O)
RAS(area 3DRAM,SDRAM upper 32MB address)/I/O port E[2]
106
RAS3L/PTJ[0]
O/(I/O)
RAS(area 3DRAM,SDRAM upper 32MB address)/I/O port J[0]
119
RAS2U/PTE[1]
O/(I/O)
RAS(area 2DRAM,SDRAM upper 32MB address)/I/O port E[1]
107
RAS2L/PTJ[1]
O/(I/O)
RAS(area 2DRAM,SDRAM upper 32MB address)/I/O portJE[1]
108
CASLL/CAS/PTJ[2]
O/(I/O)
CAS(DRAM)/CAS(SDRAM)/I/O port J[2] for D7-D0.
110
CASLH/PTJ[3]
O/(I/O)
CAS(DRAM)/I/O port J[3] for D15-D18.
112
CASHL/PTJ[4]
O/(I/O)
CAS(DRAM)/I/O port J[4] for D23-D16.
113
CASHH/PTJ[5]
O/(I/O)
CAS(DRAM)/I/O port J[5] for D31-D24.
116
CAS2L/PTE[6]
O/(I/O)
CAS(area 2DRAM)/I/O port E[6] for D7-D0.
117
CAS2H/PTE[3]
O/(I/O)
CAS(area 2DRAM)/I/O port E[3] for D15-D8.
89
WE0/DQMLL
O
D7-D0 selection signal/DQM(SDRAM)
90
WE1/DQMLU/WE
O
D15-D8 selection signal/DQM(SDRAM)/PCMCIA WE
91
WE2/DQMUL/
O/(I/O)
D23-D16 selection signal/DQM(SDRAM)/PCMCIA I/O port K[6]
ICIORD/PTK[6]
92
WE3/DQMUU/
O/(I/O)
D31-D24 selection signal/DQM(SDRAM)/PCMCIA I/O write/I/O port K[7]
ICIOWR/PTK[7]
93
RD/WR
O
Read/write change signal
88
RD
O
Read strobe
105
CKE/PTK[5]
O/(I/O)
CK enable(Only for SDRAM)/I/O port K[5]
123
WAIT
I
Hardware weight demand.
11-8
IRL[3:0]/IRQ[3:0]/
I
External interruption demand/I/OportH[3:0]
PTH[3:0]
12
IRQ4/PTH[4]
I
External interruption demand/I/OportH[4]
7
NMI
I
Non maskable interruption demand.
160
IRQOUT
O
Interruption demand output
182
WAKEUP/PTD[3]
O/(I/O)
Interruption demand output at the time of standby mode/I/OportD[3]
159
TCLK/PTH[7]
I/O
Clock input output/I/OportH[7] for TMU/RTC.
191
DREQ0/PTD[4]
I
DMA demand 0/I/OportD[4]
114
DACK0/PTD[5]
O/(I/O)
DMA acknowledge 0/I/O port D[5]
192
DREQ1/PTD[6]
I
DMA demand 0/I/O port D[6]
115
DACK1/PTD[7]
O/(I/O)
DMA acknowledge 1/I/O port D[7]
189
DRAK0/PTD[1]
O/(I/O)
DMA acknowledge 0/I/O port D[1]
190
DRAK1/PTD[0]
O/(I/O)
DMA acknowledge 0/I/O port D[0]
171
RxD0/SCPT[0]
I
Input port [0] for receiving data 0/SCI.
164
TxD0/SCPT[0]
O
Output port [0] for transmission data 0/SCI.
165
SCK0/SCPT[1]
I/O
I/O port [1] for serial clock 0/SCI.
172
RxD1/SCPT[2]
I
Input port [2] for receiving data 1/SCI.
166
TxD1/SCPT[2]
O
Output port [2] for transmission data 1/SCI.
167
SCK1/SCPT[1]
I/O
I/O port [3] for serial clock 1/SCI.
174
RxD2/SCPT[4]
I
Input port [4] for receiving data 2/SCI.
168
TxD2/SCPT[4]
O
O
utput port [4] for transmission data 2/SCI.
169
SCK2/SCPT[5]
I/O
I/O port [5] for serial clock 2/SCI.
170
RTS2/SCPT[6]
O/(I/O)
Requests to Send 2/for SCI/I/O port [6]
176
CTS2/IRQ5/SCPT[7]
I
Transmitting clearance 2/an external interruption demand/Input port [7] for SCI.
104
CE2B/PTE[5]
O/(I/O)
Chip enable 2/I/O port E[5] for Pc card 0.
126
IOIS16/PTG[7]
I
Write protection/Input port G[7]
103
CE2A/PTE[[4]
O/(I/O)
Chip enable 2/I/O port E[4] for PC card 1.
146,149"
CAP[1:2]
—
External capacity terminal for PLL [1:2]
156
EXTAL
I
External clock/Crystal oscillation element terminal
155
XTAL
O
Crystal oscillation element terminal
162
CKIO
I/O
System clock input and output
5
EXTAL2
I
Crystal oscillation element terminal for RTC.
Pin No
.
Pin Name
I/O
Pin Function
4
XTAL
O
Crystal oscillation element terminal for RTC.
193
RESETP
I
Power-on reset demand
124
RESETM
I
Manual reset demand
122
BREQ
I
B
us demand
121
BACK
O
Bus acknowledge.
2,1,144
MD[2:0]
I
Clock mode setup
196,195
MD[4:3]
I
A
rea 0 bus wide setup.
197
MD5
I
Endian setup
194
CA
O
Chip active.
158,157
STATUS[1:0]/
I/O
Processor status[1:0]/I/O port J[7:6]
PTJ[7:6]
204-199
AN[5:0]/PTL[6:7]
I
A/D conversion input[5:0]/input port L[5:0]
206,207
AN[6:7]/DA[1:0]/
I/O
A/D conversion input[6:7]/D/A conversion output[1:0]/input port L[6:7]
PTL[6:7]
177-180,185-188
PTC[7:0]/PINT[7:0]
I/O
I/O port C[7:0]/port Interruption [7:0]
184
PTD[2]/RESETOUT
I/O
I/O port D[2]/reset output
120,94
PTE[0]/PTE[7]
I/O
I/O port E[0]/I/O port E[7]
136-143
PTF[7:0]/PINT[15:8]
I
I/O port F[7:0]/port Interruption [15:8]
127-131,135
PTG[6:0]
I
I/O port G[6:0]
125
PTH[5]/ADTRG
I
I/O port H[5]/Analog trigger
151
PTH[6]
I
I/O port H[6]
21,29,35,47,59,71,
Vcc
—
power supply (3.3V)
81,85,97,111,134,
154,163,175,183,
145,150
Vcc(PLL)
—
power supply (3.3V)
3
Vcc(RTC)
—
power supply (3.3V)
205
Avcc
—
Analog power supply (3.3V)
19,27,33,45,57,
Vss
—
power supply (0V)
69,79,83,95,109,
132,152,153,161,
173,181
147,148
Vss(PLL)
—
power supply (0V)
6
Vss(TRC)
—
power supply (0V)
198,208
Avss
—
Analog power supply (0V)
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