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Model
LC-52XD1E (serv.man6)
Pages
24
Size
1.55 MB
Type
PDF
Document
Service Manual
Brand
Device
TV / LCD / Major IC Informations
File
lc-52xd1e-sm6.pdf
Date

Sharp LC-52XD1E (serv.man6) Service Manual ▷ View online

LC-46/52XD1E-RU
7 – 17
11. IC301/302: VHITDA8931T-1
SOUND AMP
12. IC705: VHIRM4020++-1
Switching Regurator
13. IC704: VHIRM4040++-1
Switching Regurator
14. IC701: VHIFA5501AN-1Y
POWER FACTOR CONTROL
Pin No.
Pin Name
I/O
Pin Function
1
VSSD
-
negative digital supply voltage; heat spreader
2
VSSA
-
Negative analogue supply voltage.
3
INN
I
inverting input.
4
INP
I
non inverting input.
5
VDDA
-
positive analog supply voltage.
6
POWERUP
I
power-up input.
7
ENABLE
I
enable input.
8
DIAG
O
diagnostic output.
9
CGND
-
control ground; reference ground for pins POWERUP, ENABLE and DIAG.
10
VSSD
-
negative digital supply voltage; heat spreader.
11
VSSD
-
negative digital supply voltage; heat spreader.
12
OVP
I
overvoltage protection reference input.
13
HVP
O
half supply voltage output for charging SE capacitor.
14
STABI
I
decoupling of internal stabilizer.
15
VSSP
-
negative power supply voltage.
16
OUT
O
PWM output.
17
BOOT
I
bootstrap capacitor connection.
18
VDDP
-
positive power supply voltage.
19
HVPI
I
half supply voltage output for reference voltage of input circuitry.
20
VSSD
-
negative digital supply voltage; heat spreader.
Pin No.
Pin Name
I/O
Pin Function
1
Z/C
I
Zero Current Detection Terminal.
2
F/B
I
Feed Back Terminal.
3
GND
-
Ground Terminal.
4
VCC
-
VCC Terminal.
5
Emitter/OCL
O
Emitter/OCL Terminal.
7
VIN
I
VIN Terminal.
8
Collector
I
Collector Terminal.
Pin No.
Pin Name
I/O
Pin Function
1
Z/C
I
Zero Current Detection Terminal.
2
F/B
I
Feed Back Terminal.
3
GND
-
Ground Terminal.
4
VCC
-
VCC Terminal.
5
Emitter/OCL
O
Emitter/OCL Terminal.
7
VIN
I
VIN Terminal.
8
Collector
I
Collector Terminal.
Pin No.
Pin Name
I/O
Pin Function
1
FB
I
Input terminal of converter out put   valtage.
2
COMP
O
Output terminal of error margin amplifier.
3
MUL
I
Input termianl of sine wave AC power wave form.
4
IS
I
Input terminal to detect current of MOSFET.
5
ZCD
I
Input termial to detect current of inductor returning to 0.
6
GND
-
Power supply ground terminal.
7
OUT
O
Output terminal to drive MOS FET directry.
8
VCC
-
Power supply input terminal to operate IC.
LC-46/52XD1E-RU
7 – 18
15. IC4001: RH-IXB680WJZZ
DIGITAL-PROCESSOR
Pin No.
Pin Name
I/O
Pin Function
NET NAME
A8,B8,B19,B20,C8,
D8,F1-F4,U23,U24,
V1-V4,AA23-AA26,
AC7,AC15,AD7,    
AD15,AE7,AE15,AF7,AF15
VDD
-
1.8 V power supply
P1.8V
B22,C3,C4,C10,D3,D4,D10,
E4,G25,M1-M4,W23,W24,
AC3,AC4,AC13,AC19,AC23,
AC24,AD3,AD4,AD10,
AD13,AD19,AD23,AD24
VDD3
-
3.3 V power supply
P3.3V
AD6
RTCVDD
-
Low power controller 1.8 V power supply
P1.8V
B13,B21,D25,K10-K17,L10-
L17,M10-M17,N10-
N17,P10-P17,R10-R17,T10-
T17,U10-U17
GND
-
Ground for power supplies
GND
C4
Others
Typical load, but the maximum is 75 pF.
S8
SDRAM/EMI
Typical load, but the maximum is 75 pF.
S8b
SDRAM/EMI
Typical load, but the maximum is 75 pF.
E8
EMI (programmable)
Typical load, but the maximum is 75 pF.
P4
PIO
Typical load, but the maximum is 75 pF.
AE11
VDDVDACRGB
-
3.3 V power supply for RGB video DAC
VDDDAC
AE9
VDDVDACYCC
-
3.3 V power supply for YCC video DAC
VDDDAC
AD11
GNDVDACRGB
-
Ground for RGB video DAC
GNDDAC
AD9
GNDVDACYCC
-
Ground for YCC video DAC
GNDDAC
AD8
SHIELDVDAC
-
Shield ground for 2 x video DACs
GND A
AE10
IREFDACRGB
-
RGB video DAC current reference
YOUT
AE8
IREFDACYCC
-
YCC video DAC current reference
AC9
VREFDACRGB
-
RGB video DAC voltage reference
AC8
VREFDACYCC
-
YCC video DAC voltage reference
A10
VDDVPLL
-
3.3 V power for video PLL
VDDPLL
C13
VDDAUDIOFSYN
-
1.8 V dedicated power for low jitter audio clock frequency synthe-
sizer
VDDF3
B12
GNDAUDIOFSYN
-
Dedicated ground for low jitter audio clock frequency synthesizer
GNDF3
C12
VDDGENFSYN
-
1.8 V dedicated power for nonaudio clock frequency synthesizer
VDDF3
B11
GNDGENFSYN
-
Dedicated ground for nonaudio clock frequency synthesizer
GNDF3
AA4
VDDAADAC
-
3.3 V power for audio DAC
VDDADCA
AA2
VSSAADAC
-
Ground for audio DAC command switches
GNDADAC
Y4
VDDASADAC
-
3.3 V power for audio DAC substrate
VDDADAC
AB2
VCCAADAC
-
3.3 V power for audio DAC command switches
VDDA
AB3
GNDAADAC
-
Ground for audio DAC
GNDADAC
AC2
VCCASADAC
-
3.3 V power for audio DAC command switches
substrate
VDDA
AD2
IREF
I
Audio DAC output reference current
AE2
VBGFIL
I
Audio DAC filtered output reference voltage
VBGFIL
AF4
LPCLKIN
I
Low power clock input (1.8 V tolerant)
CLOCK IN
AF5
LPCLKOSC
I/O
Low power clock oscillator (1.8 V tolerant)
CLOCK
A16
NO32XTAL1
I
Select for 32 kHz clock source 
 0: XTAL,      1: Internal divider
TCK
A13
CLK27MA
I
Selectable input clock to PLL or for x1 mode (5 V tolerant)
CLK27MHZ
A11
CLKSPEEDSEL
I
PLL speed select (5 V tolerant)
A12
AUXCLKOUT
O
Auxiliary clock for general use (5 V tolerant)
AF6
notRESET
I
System reset (1.8 V tolerant)
SYSRESET
AD14
notWDOGRSTOUT
O
Internal watchdog timer reset (5 V tolerant)
AE14
TDI
I
Boundary scan test data input (5 V tolerant)
TDI
AC14
TMS
I
Boundary scan test mode select (5 V tolerant)
TMS
AF16
TCK
I
Boundary scan test clock (5 V tolerant)
TCK
AF14
notTRST
I
Boundary scan test logic reset (5 V tolerant)
NOTTRST
AE13
TDO
O
Boundary scan test data output (5 V tolerant)
TDO
P1
DCUTRIGGERIN
I
External trigger input to DCU (5 V tolerant)
TRIGIN
P3
DCUTRIGGEROUT
O
Signal to trigger external debug circuitry (5 V tolerant)
TRIGOUT
C23
TSIN2LBYTECLK
I/O
Transport stream bit clock (5 V tolerant)
TS2CLK
C22
TSIN2LBYTECLKVA
LID
I/O
Transport stream bit clock valid edge (5 V tolerant)
TS2VAL
LC-46/52XD1E-RU
7 – 19
B23
TSIN2LERROR
I/O
Transport stream packet error (5 V tolerant)
D19
TSIN2LPACKETCLK
I/O
Transport stream packet strobe (5 V tolerant)
TS2STRT
B18,C18,D18,C19,C20,D20,
C21,D21
TSIN2LDATA[7:0]
I/O
Transport stream data (5 V tolerant)
TS2D[7:0]
P23
TSIN1BYTECLK
I
Transport stream bit/byte clock (5 V tolerant)
FECLK
M24
TSIN1BYTECLKVALI
D
I
Transport stream bit/byte clock valid edge (5 V tolerant)
FEVALID
M26
TSIN1ERROR
I
Transport stream packet error (5 V tolerant)
FEERROR
N26
TSIN1PACKETCLK
I
Transport stream packet strobe (5 V tolerant)
FESTROUT
K26,J25,H24,J24,L26,L25,
L24,M23
TSIN1DATA[7:0]
I
Transport stream data in (5 V tolerant)
FED[7:0]
L3
notEMIRAS or
notCI_IORD1
O
Row address strobe for SDRAM
EMIRAS
K1
not_EMICAS or
not_CI_IOW1
O
Column address strobe for SDRAM
EMICAS
J1
notEMICSA
O
Peripheral chip select A
EMICSO
K3
notEMICSB
O
Peripheral chip select B
K2
notEMICSC
O
Peripheral chip select C
N4
notEMICSD
O
Peripheral chip select D
EMICS3
J2
notEMICSE
O
Peripheral chip select E
L2
notEMICSF
O
Peripheral chip select F
EMICS5
L1, N3
notEMIBE[1:0]
O
External device data bus byte enable. 1 bit per byte of the data 
bus.
EMIBE1,
EMIRAS
N1
notEMIOE or
not_CI_OE
O
External device output enable.
EMIOE
N2
notEMILBA or
notCI_Wea
O
Flash device load burst address.
EMILBA
P4
EMIWAITnot-
TREADY
I
External memory device target ready indicator (5 V tolerant)
CPUWAIT
P2
EMIRDnotWR
O
External read/write access indicator. Common to all devices.
EMIRW
H3,H2,G2,H4,G4,E2,E1,E3,
H1,D1,D2,C2,G3,C1,B1,A1
EMIDATA[15:0]
I/O
External common data bus.
EMID[15-0]
D5,C5,D6,B3,A2,B2,A3,B4,
A4,C6,B5,A5,D7,C7,B6,A6,
B7,A7,D9,C9,B9,A9,B10,
C11
EMIADDR[25:2]
O
External common address bus
EMIA[23-2]
(D5,C5=NC)
J3
notEMIREQGNT
O
Bus request/grant indicator
NC
K4
notEMIACKREQ
I
Bus grant/request indicator (5 V tolerant)
L4
EMIBOOTMODE0
I
External power-up port size indicator (5 V tolerant)
G1
EMISDRAMCLK
O
SDRAM clock
EMICLK
J4
EMIFLASHCLK
O
Peripheral clock
NC
W1,U4,U2,U1,R2,R1,T2,T1
PIO0[7:0]
I/O
Parallel input/output pin or alternative function (5 V tolerant)
(U1:MUTE,R2:VIDEOOFF,R1:MDMRESET,T2:FERE-
SET,T1:CIRESET)
AB4,Y2,AA1,Y1,W3,U3,W2,
W4
PIO1[7:0]
I/O
(W2:TVRX,W4:TVTX)
AF3,AD5,AE3,AE5,AF2,Y3,
AA3,AF1
PIO2[7:0]
I/O
(AF3:ASPECT,AD5:IRQ,AA3:GPIO1,AF1:GPIO0)
AE18,AE4,AC16,AC12,AE6,
AC11,AC5,AE12
PIO3[7:0]
I/O
(AE6:TVSCL,AC11:TVSDA,AC5:I2CSCL,AE12:I2CSDA)
AE20,AD20,AF20,AE19,
AC17,AD18,AD17,AF19
PIO4[7:0]
I/O
(AE20:27MHzPWM,)
AC22,AF22,AD21,AC21,
AE21,AC18,AC20,AF21
PIO5[7:0]
I/O
(AD21:RXD,AC21:TXD,AF21:IR)
AF17
SCLK
O
Serial clock (5 V tolerant)
NC
AE17
PCMDATA1
O
PCM data out (5 V tolerant)
NC
AE16
PCMCLK
I/O
External PCM clock input or internal PCM clock output (5 V toler-
ant)
NC
AF18
LRCLK
O
Left/right clock (5 V tolerant)
TL4027
AD16
SPDIF
O
Digital audio output (5 V tolerant)
SPDIF
AD26,AB25,AB24,AC25,
AE26,AB23,AE25,AF26,
AD25,AF25,AE24,AF24,
AF23,AE23
SMIADDR[13:0]
O
SDRAM address bus
SMIA[13-0]
U26,U25,R23,V26,V25,T23,
V24,V23,W26,W25,Y25,
Y26,Y23,AB26,Y24,AC26
SMIDATA[15:0]
I/O
SDRAM data bus
SMID[15-0]
T24
notSMICS0
O
SDRAM chip select for 1st SDRAM
SMICS
LC-46/52XD1E-RU
7 – 20
T25
notSMICS1
O
SDRAM chip select for 2nd 16 Mbit SDRAM
T26
notSMICAS
O
SDRAM column address strobe
SMICAS
R24
notSMIRAS
O
SDRAM row address strobe
SMIRAS
R25
notSMIWE
O
SDRAM write enable
SMIWE
P26
SMIMEMCLKIN
I
SDRAM memory clock input
R26
SMIMEMCLKOUT
O
SDRAM memory clock output
SMICLK
P24
SMIDATAML
O
SDRAM data bus lower byte enable
SMIDQML
P25
SMIDATAMU
O
SDRAM data bus upper byte enable
SMIDQMI
B15,A15,D16,C16,B16,B17,
C17,D17
P1284DATA[7:0]
I/O
1284 AV data (5 V tolerant)
NC
C15
notP1284SELECTIN
I/O
1284 AV control signals (5 V tolerant)
NC
D15
notP1284INIT
I/O
NC
A14
notP1284FAULT
I/O
NC
B14
notP1284AUTOFD
I/O
NC
C14
P1284SELECT
I/O
NC
D14
P1284PERROR
I/O
NC
D13
P1284BUSY
I/O
NC
D12
notP1284ACK
I/O
NC
D11
notP1284STROBE
I/O
NC
T4, R4, T3,R3
INTERRUPT[3:0]
I/O
External interrupts (5 V tolerant)
MODEMIRQ,
TL4003,
CIIRQ1,
CIIRQ0
AE1
OUTPLEFT
O
Left channel, differential positive current output
LEFTP
AC1
OUTMLEFT
O
Left channel, differential negative current output
LEFTM
AD1
OUTPRIGHT
O
Right channel, differential positive current output
RIGHTP
AB1
OUTMRIGHT
O
Right channel, differential negative current output
RIGHTM
AF12
ROUT
O
Red output
R
AF11
GOUT
O
Green output
G
AF13
BOUT
O
Blue output
B
AF8
COUT
O
Chroma output
COUT
AF9
CVOUT
O
Composite video output
CVBS
AF10
YOUT
O
Luma output
YOUT
AD22
notHSYNC
I/O
Horizontal sync (5 V tolerant)
NC
AE22
EVENnotODD
I/O
Vertical sync (5 V tolerant)
TL4016
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