Sharp LC-52XD1E (serv.man6) Service Manual ▷ View online
LC-46/52XD1E-RU
7 – 9
61
AVSS
-
Analog Ground for IF Part.
GND
62
AVSS
-
Analog Ground for IF Part.
GND
63
NC -
Not
Connected.
N.C.
64
NC -
Not
Connected.
N.C.
65
AVSUP
-
Analog Power Supply +5V.
+5V
66
AVSUP
-
Analog Power Supply +5V.
+5V
67
ANA_IN1 +
I
IF Input 1.
SIF-IN
68
ANA_IN -
I
IF Common (can be Left vacant only if lF input 1 is not used)
ANA-IN-
69
ANA_IN2 +
I
IF Input2 (can be left vacant only if lF input 1 is not used)
ANA-IN2+
70
TESTEN
-
Test Pin (imust be connected to ground)
GND
71
XTAL_IN
I
Crystal Oscillator Input.
XTAL-IN
72
XTAL_OUT O
Crystal
Oscillator Output.
XTAL-OUT
73
TP I
Test
Input.
N.C.
74
AUD_CL_OUT
O
Audio Clock Output (18.432MHz)
N.C.
75
NC -
Not
Connected.
N.C.
76
SPDIF_OUT O
S/PDIF
Output.
N.C.
77
DCTRI/O_1
I/O
Digital Control Port 1.
N.C.
78
DCTRI/O_0
I/O
Digital Control Port 0.
N.C.
79
ADR_SEL
I
I2C Address Select.
GND
80
STANDBYQ
-
Standby (active low)
+5V
LC-46/52XD1E-RU
7 – 10
7. IC3301: FRC RH-IXB064WJ (FRC9429A)
FRAME RATE CONVERTER
Pin No.
Pin Name
I/O
Pin Function
1
NC
-
No Connection
2
NC
-
Test, do not use
3
656I1/YIN1
I
Digital (luminance) input
4
656I2/YIN2
I
Digital (luminance) input
5
VIN
I
Vertical sync input
6
656I3/YIN3
I
Digital (luminance) input
7
656I4/YIN4
I
Digital (luminance) input
8
VDDP0
S
Supply digital pad (3.3 V)
9
VSSP0
S
Supply digital pad (0 V)
10
HIN
I
Horizontal sync input
11
656I5/YIN5
I
Digital (luminance) input
12
656I6/YIN6
I
Digital (luminance) input
13
656I7/YIN7
I
Digital (luminance) input [MSB]
14
CLKIN
I
Clock input (max. 81.0 MHz)
15
VDDD0
S
Supply digital pad (1.8 V)
16
VSSD0
S
Supply digital pad (0 V)
17
AVI
I
Active video input
18
VDDAPLL
S
Supply analog PLL (1.8 V)
19
VSSAPLL
S
Supply analog PLL (0 V)
20
VSSD1
S
Supply digital core (0 V)
21
VDDD10
S
Supply digital core (1.8 V)
22
VDDD11
S
Supply digital core (1.8 V)
23
XIN
I
Crystal connection 1
24
XOUT
O
Crystal connection 2
25
VSSP1
S
Supply digital pad (0 V)
26
VDDP1
S
Supply digital pad (3.3 V)
27
RGBOUT9
O
Tristate (SELOMODE=0)
Digital (red: SELRB=0; blue: SELRB=1;)
Output [MSB](SELOMODE=1)
Digital (red: SELRB=0; blue: SELRB=1;)
Output [MSB](SELOMODE=1)
28
RGBOUT8
O
Tristate (SELOMODE=0)
Digital (red: SELRB=0; blue: SELRB=1;)
Output (SELOMODE=1)
Digital (red: SELRB=0; blue: SELRB=1;)
Output (SELOMODE=1)
29
RGBOUT7
O
Tristate (SELOMODE=0)
Digital (red: SELRB=0; blue: SELRB=1;)
Output (SELOMODE=1)
Digital (red: SELRB=0; blue: SELRB=1;)
Output (SELOMODE=1)
30
RGBOUT6
O
Tristate (SELOMODE=0)
Digital (red: SELRB=0; blue: SELRB=1;)
Output (SELOMODE=1)
Digital (red: SELRB=0; blue: SELRB=1;)
Output (SELOMODE=1)
31
RGBOUT5
O
Tristate (SELOMODE=0)
Digital (red: SELRB=0; blue: SELRB=1;)
output (SELOMODE=1)
Digital (red: SELRB=0; blue: SELRB=1;)
output (SELOMODE=1)
32
RGBOUT4
O
Tristate (SELOMODE=0)
Digital (red: SELRB=0; blue: SELRB=1;)
Output (SELOMODE=1)
Digital (red: SELRB=0; blue: SELRB=1;)
Output (SELOMODE=1)
33
AVO/ITR
O
Active video output (CPUIRQ=0)
Interrupt signal output from
Interrupt signal output from
μC (CPUIRQ=1)
Static 0 (CPUIRQ=2)
Static 1 (CPUIRQ=3)
Static 1 (CPUIRQ=3)
34
VOUT
O
Vertical sync output
35
HOUT
O
Horizontal sync output.
(Synchronized to 40.5-81 MHz CLKOUTSEL72=1)
(Synchronized to 20.25-40.5 MHz
CLKOUTSEL72=0 and CLKOUTSEL=1)
(Synchronized to 15.1875-30.75 MHz
CLKOUTSEL72=0 and CLKOUTSEL=0)
(Synchronized to 40.5-81 MHz CLKOUTSEL72=1)
(Synchronized to 20.25-40.5 MHz
CLKOUTSEL72=0 and CLKOUTSEL=1)
(Synchronized to 15.1875-30.75 MHz
CLKOUTSEL72=0 and CLKOUTSEL=0)
36
CLKOUT
O
Output clock disabled (CLKOUTON=0)
Output clock (max. 81 MHz) (CLKOUT=1)
(40.5-81 MHz CLKOUT72=1
20.25-40.5 MHz CLKOUT72=0 and CLKOUTSEL=1
1515.1875-30.37 MHz CLKOUT72=0 and
CLKOUTSEL=0)
Output clock (max. 81 MHz) (CLKOUT=1)
(40.5-81 MHz CLKOUT72=1
20.25-40.5 MHz CLKOUT72=0 and CLKOUTSEL=1
1515.1875-30.37 MHz CLKOUT72=0 and
CLKOUTSEL=0)
37
VSSP2
S
Supply digital pad (0 V)
38
VDDP2
S
Supply digital pad (3.3 V)
39
RESET
I
Reset input
LC-46/52XD1E-RU
7 – 11
40
RGBOUT3
O
Tristate (SELOMODE=0)
Digital (red: SELRB=0; blue: SELRB=1;)
Output (SELOMODE=1)
Digital (red: SELRB=0; blue: SELRB=1;)
Output (SELOMODE=1)
41
RGBOUT2
O
Tristate (SELOMODE=0)
Digital (red: SELRB=0; blue: SELRB=1;)
Output (SELOMODE=1)
Digital (red: SELRB=0; blue: SELRB=1;)
Output (SELOMODE=1)
42
RGBOUT1
O
Tristate (SELOMODE=0)
Digital (red: SELRB=0; blue: SELRB=1;)
Output (SELOMODE=1)
Digital (red: SELRB=0; blue: SELRB=1;)
Output (SELOMODE=1)
43
RGBOUT0
O
Tristate (SELOMODE=0)
Digital (red: SELRB=0; blue: SELRB=1;)
Output [LSB] (SELOMODE=1)
Digital (red: SELRB=0; blue: SELRB=1;)
Output [LSB] (SELOMODE=1)
44
YOUT9
O
Tristate (ENITUE=0)
Digital (luminance/green) output [MSB] (ENITUE=1)
Digital (luminance/green) output [MSB] (ENITUE=1)
45
YOUT8
O
Tristate (ENITUE=0)
Digital (luminance/green) output (ENITUE=1)
Digital (luminance/green) output (ENITUE=1)
46
YOUT7
O
Tristate (ENITUE=0)
Digital (luminance/green) output (ENITUE=1)
Digital (luminance/green) output (ENITUE=1)
47
VDDD2
S
Supply digital core (1.8 V)
48
VSSD2
S
Supply digital core (0 V)
49
VDDP3
S
Supply digital pad (3.3 V)
50
VSSP3
S
Supply digital pad (0 V)
51
NC
-
No Connection
52
YOUT6
O
Tristate (ENITUE=0)
Digital (luminance/green) output (ENITUE=1)
Digital (luminance/green) output (ENITUE=1)
53
YOUT5
O
Tristate (ENITUE=0)
Digital (luminance/green) output (ENITUE=1)
Digital (luminance/green) output (ENITUE=1)
54
VSSP4
S
Supply digital pad (0 V)
55
YOUT4
O
Tristate (ENITUE=0)
Digital (luminance/green) output (ENITUE=1)
Digital (luminance/green) output (ENITUE=1)
56
VDDP4
S
Supply digital pad (3.3 V)
57
YOUT3
O
Tristate (ENITUE=0)
Digital (luminance/green) output (ENITUE=1)
Digital (luminance/green) output (ENITUE=1)
58
YOUT2
O
Tristate (ENITUE=0)
Digital (luminance/green) output (ENITUE=1)
Digital (luminance/green) output (ENITUE=1)
59
YOUT1
O
Tristate (ENITUE=0)
Digital (luminance/green) output (ENITUE=1)
Digital (luminance/green) output (ENITUE=1)
60
YOUT0
O
Tristate (ENITUE=0)
Digital (luminance/green) output [LSB] (ENITUE=1)
Digital (luminance/green) output [LSB] (ENITUE=1)
61
CLKF20
O
Output clock 20.25 MHz disabled (CLKF20ON=0)
Output clock 20.25 MHz enabled (CLKF20ON=1)
Output clock 20.25 MHz enabled (CLKF20ON=1)
62
UVOUT9
O
Tristate (ENITUE=0)
Digital (chrominance/blue) output [MSB] (ENITUE=1and SELRB=0)
Digital (chrominance/red) output [MSB] (ENITUE=1and SELRB=1)
Digital (chrominance/blue) output [MSB] (ENITUE=1and SELRB=0)
Digital (chrominance/red) output [MSB] (ENITUE=1and SELRB=1)
63
VSSD30
S
Supply digital core (0 V)
64
VSSD31
S
Supply digital core (0 V)
65
VDDD30
S
Supply digital core (1.8 V)
66
VDDD31
S
Supply digital core (1.8 V)
67
UVOUT8
O
Tristate (ENITUE=0)
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
68
UVOUT7
O
Tristate (ENITUE=0)
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
69
VSSP50
S
Supply digital pad (0 V)
70
VSSP51
S
Supply digital pad (0 V)
71
VSSP52
S
Supply digital pad (0 V)
72
VDDP5
S
Supply digital pad (3.3 V)
73
UVOUT6
O
Tristate (ENITUE=0)
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
74
NC
-
No Connection
75
NC
-
No Connection
76
UVOUT5
O
Tristate (ENITUE=0)
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
77
NC
-
No Connection
LC-46/52XD1E-RU
7 – 12
78
UVOUT4/
INTR
INTR
O
Tristate ( ENITUE=0)
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
Interrupt signal output from
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
Interrupt signal output from
μC (CPUIRQ=5)
Static 0 (CPUIRQ=6)
Static 1 (CPUIRQ=7)
Static 1 (CPUIRQ=7)
79
VDDP6
S
Supply digital pad (3.3 V)
80
VSSP6
S
Supply digital pad (0 V)
81
UVOUT3
O
Tristate (ENITUE=0)
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
82
UVOUT2
O
Tristate (ENITUE=0)
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
83
UVOUT1
O
Tristate (ENITUE=0)
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
84
UVOUT0
O
Tristate (ENITUE=0)
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
85
VDDD4
S
Supply digital core (1.8 V)
86
VSSD4
S
Supply digital core (0 V)
87
VDDA0
S
Supply analog DAC SVM (3.3 V)
88
ASVMOUT
O
Middle level (STANDBY=1)
Analog SVM output (ACTFBL=0 and STANDBY=1)
Analog SVM output (control by SVMOFF possible)
(ACTFBL=1 and STANDBY=0)
Analog SVM output (ACTFBL=0 and STANDBY=1)
Analog SVM output (control by SVMOFF possible)
(ACTFBL=1 and STANDBY=0)
89
VSSA0
S
Supply analog DAC SVM (0 V)
90
VDDA1
S
Supply analog DAC B/U (3.3 V)
91
AUOUT
O
Middle level (STANDBY=0)
Chrominance output (STANBY=1)
Chrominance output (STANBY=1)
92
VSSA1
S
Supply analog DAC B/U (0 V)
93
VDDA2
S
Supply analog DAC G/Y (3.3 V)
94
AYOUT
O
Middle level (STANDBY=0)
Luminance output (STANDBY=1)
Luminance output (STANDBY=1)
95
VSSA2
S
Supply analog DAC G/Y (0 V)
96
VDDA3
S
Supply analog DAC R/V (3.3 V)
97
AVOUT
O
Middle level (STANDBY=0)
Chrominance output (STANDBY=1)
Chrominance output (STANDBY=1)
98
VSSA3
S
Supply analog DAC R/V (0 V)
99
VSSA4
S
Supply analog band gap (0 V)
100
VDDA4
S
Supply analog band gap (3.3 V)
101
VSSD5
S
Supply digital core (0 V)
102
VDDD5
S
Supply digital core (1.8 V)
103
NC
-
No Connection
104
NC
-
No Connection
105
SCL
I/O
I2C bus clock
106
SDA
I/O
I2C bus data
107
NC
-
No Connection
108
NC
-
No Connection
109
VSSP7
S
Supply digital pad (0 V)
110
VDDP7
S
Supply digital pad (3.3 V)
111
TMS
I
Test mode select (3.3 V)
112
NC
-
No Connection
113
TDO/
SVMOFF
SVMOFF
O/I
Test data out (ACTSVMOFF=1)
SVM input signal (ACTSVMOFF=0)
SVM input signal (ACTSVMOFF=0)
114
TDI
I
Test data in (0V)
115
TCLK
I
Test clock (3.3 V)
116
INTR
O
Interrupt signal
Static 0 (CPUIRQ2=00)
Static 1 (CPUIRQ2=01)
Interrupt signal output from
Static 0 (CPUIRQ2=00)
Static 1 (CPUIRQ2=01)
Interrupt signal output from
μC (CPUIRQ2= 1x)
117
656I02
I
Digital (luminance) input [LSB]
118
656I12
I
Digital (luminance) input
119
656I22
I
Digital (luminance) input
120
656I32
I
Digital (luminance) input
121
656I42
I
Digital (luminance) input
122
656I52
I
Digital (luminance) input
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