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LC-46/52XD1E-RU

7 – 5

256Mb DDR SDRAM

Pin No.

Pin Name

I/O

Pin Function

45,46

CK, 

I

Clock : CK and 

 are differential clock inputs.

All address and control input signals are sampled on the positive edge of CK and negative edge of CK.

Output (read) data is referenced to both edges of 

.

Internal clock signals are derived from CK/

.

44

CKE

I

Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, 
and device input buffers and output drivers.
Taking CKE Low provides PRECHARGE POWER DOWN and SELF REFRESH 
operction(all bank idle)
CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry.
CKE is asynchronous for SELF REFRESH exit, and for output disable.
CKE must be maintained high throughput READ and WRITE accesses.

Input buffers, excluding CK,

 and CKE are disabled during POWER-DOWN.

Input buffers, excluding CKE are disabled during SELF REFRESH. 
CKE is an SSTL_2 input, but will detect an LVCMOS Low level after Vdd is applied upon 
1st power up, After VREF has become stable during the power on and initialization 
sequence, it must be maintained for proper operation of the CKE receiver.
For proper SELF-REFRESH entry and exit, VREF must be maintained to this input.

24

I

Chip Select : 

 enables(registered LOW) and disables(registered HIGH) the command 

decoder.

All commands are masked when 

 is registered HIGH.

 provides for external bank selection on systems with multiple banks.

 is considered part of the command code.

21-23

, , I

Command Inputs : 

, 

 and 

 (along with 

) define the command being

 entered.

20,47

LDM,(UDM)

I

Input Data Mask : DM is an input mask signal for write data.
Input data is masked when DM is sampled HIGH along with that input data during a 
WRITE access.
DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ and DQS loading.
For the x16, LDM corresponds to the data on DQ0>D7 ; UDM corresponds to the 
data on DQ8>DQ15.
DM may be driven high, low, or floating during READs.

26,27

BA0, BA1

I

Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ,WRITE 
or PRECHARGE command is being applied.

28-32,

35-42

A [0 : 12]

I

Address Inputs : Provide the row address for ACTIVE commands, and the column 
address and AUTO PRECHARGE bit for READ/WRITE commands, to select one 
location out of the memory array in the respective bank. 
A10 is sampled during a PRECHARGE command to determine whether the 
PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH).
If only one bank is to be precharged, the bank is selected by BA0, BA1. 
The address inputs also provide the op-code during a MODE REGISTER SET 
command. 
BA0 and BA1 define which mode register is loaded during the MODE REGISTER 
SET command (MRS or EMRS).

2,4,5,7,

8,10,

11,13,

54,56,
57,59,
60,62,

63,65

DQ

I/O

Data Input/Output : Data bus.

16,51

LDQS,(U)DQS

I/O

Data Strobe : Output with read data, input with write data. 
Edge-aligned with read data,centered in write data. 
Used to capture write data. 
For the x16, LDQS corresponds to the data on DQ0>D7 ; UDQS corresponds to
the data on DQ8>DQ15

14,17,
19,25,
43,50,

53,

NC

-

No Connect : No internal electrical connection is present.

3,9,15,

55,61

VDDQ

-

DQ Power Supply : +2.5V 

± 0.2V. (+2.6V ± 0.1V for DDR400)

CK

CK

CK

CK

CK

CS

CS

CS

CS
CS

RAS CAS
WE

RAS CAS

WE

CS

LC-46/52XD1E-RU

7 – 6

128Mb Flash Memory

6,12,

52,58,

64

VSSQ

-

DQ Ground.

1,18,33,

VDD

-

Power Supply : +2.5V 

± 0.2V. (+2.6V ± 0.1V for DDR400)

34,48,

66

VSS

-

Ground.

49

VREF

I

SSTL_2 reference voltage.

Pin No.

Pin Name

I/O

Pin Function

I

2-12, 

15,  

18-26,
54, 31

A0-A22

I

23 Address lnputs.    

35,37,
39,41,
44,46,

48,50

DQ0-DQ7

I/O

8 Data Inputs / Outputs.   

35-42,

44-50

DQ8-DQ14

I/O

7 Data Inputs / Outputs.   

51

DQ15A-1

I

Data Input/Output or Address Input.

32

I

Chip Enable.  

34

 

O

Output Enable.

13

I

Write Enable.  

16

I

Hardware Vpp/ Write Protect 

14

I

Reset/Block Temporary Unprotect.

17

O

Ready / Busy Output.    

53

I

Byte/Word Organization Select.

43

VCC

-

Supply Voltage

33.52

VSS

-

Ground.    

27,28,

55,56

NC

-

Not Connected Internally.    

29

VCCQ

-

Supply Voltage for Input/Output.

CE
OE

WE

Vpp/WP

RP

R/B

BYTE

LC-46/52XD1E-RU

7 – 7

16BIT D-TYPE LATCH.

Pin No.

Pin Name

I/O

Pin Function

47,46,

44,

43,41,

40,

38,37

1D1-1D8

I

Input Signal 1D1-1D8.

36,35,

33,

32,30,

29,

27,26

2D1-2D8

I

Input Signal 2D1-2D8.

1

I

Non_Output Enable Signal 1.

24

I

Non_Output Enable Signal 2.

48

1LE

I

Latch Enable Signal 1.

25

2LE

I

Latch Enable Signal 2.

2,3,5,6

,8,9,

11,12

1Q1-1Q8

O

Latch Output Signal 1Q1-1Q8.

13,14,

16,

17,19,

20,

22,23

2Q1-2Q8

O

Latch Output Signal 2Q1-2Q8.

7,18,

31,42

VCC

-

Supply Voltage.

4,10,

15,21,
28,34,

39,45

GND

-

Ground.

1OE

2OE

LC-46/52XD1E-RU

7 – 8

Multistandard Sound Processor.

Pin 

No.

Pin Name

I/O

Pin Function

NET_NAME

1

NC  

-

Not Connected. 

N.C.

2

I2C_CL

I/O

I2C Clock.

SCL5

3

I2C_DA  

I/O

I2C Data .

SDA5

4

I2S_CL  

I/O

Sync. I2S Clock. 

N.C.

5

I2S_WS 

I/O

Sync.  I2S Word Strobe .

N.C.

6

I2S_DA_OUT  

O

Sync. I2S Data Output. 

N.C.

7

I2S_DA_IN1

I

Sync. I2S Data Input 1.

N.C.

8

I2S_DEL_IN 

I

Sync. I2S Input From Delay Line. 

I2S_DEL_IN

9

I2S_DEL_OUT  

O

Sync. I2S 0utput to Extemal Delay Line. 

I2S_DEL_OUT

10

I2S_DEL_CL

O

I2S Clock Output for External Delay. 

I2S_DEL_CL

11

I2S_DEL_WS

O

I2S Word Strobe Output for External Delay. 

I2S_DEL_WS

12

DVSUP  

-

Digilal Power Supply. 

+5V

13

DVSUP  

-

Digital Power Supply .

+5V

14

DVSS  

-

Digital Ground.

GND

15

DVSS  

-

Digital Ground. 

GND

16

DVSS  

-

Digital Ground.

GND

17

I2S_DA_IN2

I

Sync. I2S Data lnput 2. 

N.C.

18

NC  

-

Not Connected. 

N.C.

19

I2S_CL3  

I/O

Async. I2S Clock lnput/Sync. 12S Clock Output. 

N.C.

20

I2S_WS3

I/O

Async. I2S Word Strobe lnput/Sync. 12S Word Strobe Output. 

N.C.

21

RESETQ  

I

Power - On Reset (active low) 

RESET_A

22

I2S_DA_IN3

I

Sync./Async. I2S Data Input3.

N.C.

23

I2S_DA_IN4

I

Sync.12S Data lnput 4. 

N.C.

24

DACA_R  

O

Aux Output, Right.

OPEN

25

DACA_L

O

Aux Output, Left. 

OPEN

26

VREF2

-

Reference Ground 2. 

GND

27

DACM_R

O

Main Output, Right  

SPKOUTR

28

DACM_L

O

Main  Output, Left. 

SPKOUTL

29

DACM_C

O

Main  Output, Center. 

N.C.

30

DACM_SUB

O

Main Output, Subwoofer.  

N.C.

31

DACM_SR

O

Surround Output, Right. 

N.C.

32

DACM_SL

O

Surround Output, Left.  

N.C.

33

SC2_OUT_R

O

SCART 2 Output, Right.  

EXT2_OUT_R

34

SC2_OUT_L

O

SCART 2 Output, Left. 

EXT2_OUT_L

35

VREF 1

-

Reference Ground 1. 

GND

36

SC1_OUT_R

O

SCART 1 Output, Right.  

EXT1_OUT_R

37

SC1_OUT_L

O

SCART 1 Output, Left. 

EXT1_OUT_L

38

CAPL_A

-

Volume Capacitor Aux . 

CAPL_A

39

AHVSUP

I

Analog Power Supply +8V.  

+8V

40

CAPL_M

-

Volume Capacitor Main.  

CAPL_M

41

SC3_OUT_R

O

SCART 3 Output, Right.  

N.C.

42

SC3_OUT_L

O

SCART 3 Output, Left. 

N.C.

43

AHVSS

-

Analog Ground.  

GND

44

AHVSS

-

Analog Ground.

GND

45

AGNDC

-

Analog Reference Voltage.  

AGNDC

46

NC

-

Not Connected.  

N.C.

47

SC4_IN_L

I

SCART 4 Input, Left. 

EXT4_IN_L

48

SC4_IN_R

I

SCART 4 Input, Right. 

EXT4_IN_R

49

ASG

-

Analog Shield Ground. 

GND

50

SC3_IN_L

I

SCART 3 Input, Left.  

EXT3_IN_L

51

SC3_IN_R

I

SCART 3 Input, Right. 

EXT3_IN_R

52

ASG

-

Analog Shield Ground.

GND

53

SC2_IN_L

I

SCART 2 Input, Left.

EXT2_IN_L

54

SC2_IN_R

I

SCART 2 Input, Right. 

EXT2_IN_R

55

ASG

-

Analog Shield Ground.

GND

56

SC1_IN_L

I

SCART 1 Input, Left.

EXT1_IN_L

57

SC1_IN_R

I

SCART 1 Input, Right. 

EXT1_IN_R

58

VREFTOP

-

Reference Voltage IF A/D Converter.

VREF TOP

59

SC5_IN_L/
MONO_IN

I

SCART 5 Input, Left/SCART Mono lnput for PMQFP64-2. 

HDMI_A_IN_L

60

SC5_IN_R 

I

SCART 5 Input, Right. 

HDMI_A_IN_R