Sharp LC-42XD10E (serv.man5) Service Manual ▷ View online
LC-42XD10E/RU
5 – 5
3. IC3002: RH-IXB755WJZZ
Video Graphics Controller
Pin No.
Pin Name
I/O
Description
M23
XIN
I
20.25MHz clock or crystal input
M22
XOUT
O
Output to a crystaI that is connected to XIN .
D18
RESET_N
I
Reset input (active low)
G15
POR_N
O
Power-on reset generator (active low), May be connected to RESET_N.
H7
TM
I
Test mode enable.
L20
VARCLK
O
Vriable clock output (e.g. FRC94xxAclk)
Y20
CV01
O
Analog video out (CVBS or Y) (EXT2-VOUT2)
Y23
CV02
O
Analog video out (CVBS or Y) (EXT1-VOUT1)
Y22
CV03
O
- (pull up)
Y21
CV04
O
- (pull up)
AA23
CV05
O
- (pull up)
AA22
CV06
O
- (pull up)
AB23
CV09
O
- (pull up)
AC23
CVI1
I
Analog video in (CVBS) (TUNER CVBS IN)
AB22
CVI2
I
Analog video in (CVBS) (EXT1 VIN1)
AC22
CVI3
I
-
AA21
CVI4
I
Analog video in (CVBS) (DVB CVBS IN)
AB20
YI1
I
Analog video in (Y or CVBS) (EXT3 CVBS IN)
AB21
YI2
I
Analog video in (Y or CVBS) (EXT2 Y/CVBS IN)
AA20
YI3
I
-
AC20
CI1
I
Analog video in (chroma) (EXT3 IN3C IN)
AC21
CI2
I
Analog video in (chroma) (EXT2 C2 IN)
AC19
CI3
I
-
Y19
RI1
I
Analog component input 1 (EXT1-RED1)
AB19
GI1
I
Analog component input 1 (EXT1-GREEN1)
AC18
BI1
I
Analog component input 1 (EXT1-BLUE1)
AA19
FBI1
I
Analog component input 1 (EXT1-FAST-SW1)
AA18
RI2
I
Analog component input2 (DVB-R)
AB18
GI2
I
Analog component input2 (DVB-G)
Y18
BI2
I
Analog component input2 (DVB-B)
AC17
FBI2
I
Analog component input2 GND
AA17
RI3
I
Analog component input3 (APC_R)
AB17
GI3
I
Analog component input3 (APC_G)
Y17
BI3
I
Analog component input3 (APC_B)
AC16
FBI3
I
Horizontal sync input. (PCV_H)
W21
VIN
I
Vertical sync input. (PCV_V)
B17
I2SWS
I
I2S word strobe (digital audio left/right select input)
C17
I2SCL
I
I2S clock (digital audio bit clock input)
D17
I2SDA1
I
I2S data input (PCM audio data)
A18
I2SDA0
O
I2S data output (PCM audio data)
L3
RAMD_31
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_31)
L4
RAMD_30
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_30)
K3
RAMD_29
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_29)
Kl
RAMD_28
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_28)
K4
RAMD_27
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_27)
J3
RAMD_26
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_26)
J4
RAMD_25
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_25)
H3
RAMD_24
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_24)
H4
RAMD_23
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_23)
G3
RAMD_22
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_22)
G4
RAMD_21
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_21)
F3
RAMD_20
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_20)
F1
RAMD_19
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_19)
G2
RAMD_18
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_18)
G1
RAMD_17
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_17)
H2
RAMD_16
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_16)
C1
RAMD_15
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_15)
D2
RAMD_14
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_14)
D1
RAMD_13
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_13)
E2
RAMD_12
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_12)
D3
RAMD_11
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_11)
E4
RAMD_10
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_10)
LC-42XD10E/RU
5 – 6
E3
RAMD_9
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_9)
F4
RAMD_8
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_8)
C7
RAMD_7
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_7)
D6
RAMD_6
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_6)
C6
RAMD_5
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_5)
D5
RAMD_4
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_4)
A7
RAMD_3
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_3)
B6
RAMD_2
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_2)
A6
RAMD_1
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_1)
B5
RAMD_0
I/O
DDR-SDRAM bi-directional data bus. (SDRAM-RAMD_0)
A2
RAMA_12
O
Address bits for DRAM. (Row/Col) (SDRAM-RAMA_12)
A3
RAMA_11
O
Address bits for DRAM. (Row/Col) (SDRAM-RAMA_11)
D8
RAMA_10
O
Address bits for DRAM. (Row/Col) (SDRAM-RAMA_10)
B3
RAMA_9
O
Address bits for DRAM. (Row/Col) (SDRAM-RAMA_9)
A4
RAMA_8
O
Address bits for DRAM. (Row/Col) (SDRAM-RAMA_8)
B4
RAMA_7
O
Address bits for DRAM. (Row/Col) (SDRAM-RAMA_7)
C3
RAMA_6
O
Address bits for DRAM. (Row/Col) (SDRAM-RAMA_6)
C4
RAMA_5
O
Address bits for DRAM. (Row/Col) (SDRAM-RAMA_5)
D4
RAMA_4
O
Address bits for DRAM. (Row/Col) (SDRAM-RAMA_4)
D9
RAMA_3
O
Address bits for DRAM. (Row/Col) (SDRAM-RAMA_3)
AlO
RAMA_2
O
Address bits for DRAM. (Row/Col) (SDRAM-RAMA_2)
B9
RAMA_1
O
Address bits for DRAM. (Row/Col) (SDRAM-RAMA_1)
C9
RAMA_0
O
Address bits for DRAM. (Row/Col) (SDRAM-RAMA_0)
C8
RAMBA_1
O
DRAM bank select (SDRAM-RAM_BA1)
D7
RAMBA_0
O
DRAM bank select (SDRAM-RAM_BA0)
B8
RAMRAS_N
O
DRAM row address strobe (active low) (SDRAM-RAMRAS_N)
A8
RAMCAS_N
O
DRAM column address strobe (active low) (SDRAM-RAMCAS_N)
J1
RAMDM_3
O
DRAM byte mask lines. (SDRAM-RAMDM_3)
J2
RAMDM_2
O
DRAM byte mask lines. (SDRAM-RAMDM_2)
F2
RAMDM_1
O
DRAM byte mask lines. (SDRAM-RAMDM_1)
C5
RAMDM_0
O
DRAM byte mask lines. (SDRAM-RAMDM_0)
B7
RAMWE_N
O
DRAM write enable (active low) (SDRAM-RAMWE_N)
A9
RAMCS_N
O
DRAM chip select (active low) (SDRAM-RAMCS_N)
A1
RAMCKE
O
DRAM clock enable. (SDRAM-RAMCKE)
B2
RAMCLK
O
DRAM clock output. (SDRAM-RAMCLK)
C2
RAMCLK_N
O
DRAM clock output (inverted) (SDRAM-RAMCLK_N)
K2
RAMDQS_3
I/O
Strobe signal. (SDRAM-RAMDQS_3)
H1
RAMDQS_2
I/O
Strobe signal. (SDRAM-RAMDQS_2)
E1
RAMDQS_1
I/O
Strobe signal. (SDRAM-RAMDQS_1)
A5
RAMDQS_0
I/O
Strobe signal. (SDRAM-RAMDQS_0)
B1
RAMCLKIN
I
Clock (RAMCLK) feed back. (SDRAM-RAMCLKIN)
G7
SSTLVREF
I
SSTL2 Reference Voltage. (SDRAM-SSTLVREF)
K20
SCL1
I
12C bus 1clock.
K21
SDA1
I/O
12C bus 1 data.
B18
SCL2
I
12C bus 2 clock. (no used)
C18
SDA2
I/O
12C bus 2 data. (no used)
H17
TRST
I
Test reset.
G17
TMS
I
Test mode select.
G8
TDO
O
Test data output.
G16 TCLK
I
Test
clock.
G9
TDl
I
Test data input.
M20
CADC5
I
CADC analog source input. (KEY-1) (to key-unit)
M21
CADC4
I
CADC analog source input. (TH3001)
L21
CADC3
I
CADC analog source input. (OPCIN)
K22
CADC2
I
CADC analog source input. (KEY-2) (to key-unit)
L22
CADC1
I
CADC analog source input. (SLOW_SW1)
L23
CADC0
I
CADC analog source input. (SLOW_SW2)
N23
DPWM1
O
Display-PWM outputs. (PWMOUT-BRT-INV)
N22
DPWM2
O
-
W23
DPWM3
O
-
W22
VITUFE
O
V sync output of lTUE-FE.
U3
NVM_22
O
NVM_[22:16] upper address bits (to-flash memory)
Pull-up and pull-down resistors must be used for boot-process configuration
Pull-up and pull-down resistors must be used for boot-process configuration
M2
NVM_21
O
NVM_[22:16] upper address bits (to-flash memory)
M4
NVM_20
O
NVM_[22:16] upper address bits (to-flash memory)
L1
NVM_19
O
NVM_[22:16] upper address bits (to-flash memory)
LC-42XD10E/RU
5 – 7
M1
NVM_18
O
NVM_[22:16] upper address bits (to-flash memory)
N4
NVM_17
O
NVM_[22:16] upper address bits (to-flash memory)
U1
NVM_16
O
NVM_[22:16] upper address bits (to-flash memory)
U4
NVM_15
I/O
NVMD_[15:0] multiplexed address/data (to-flash memory)
T1
NVM_14
I/O
NVMD_[15:0] multiplexed address/data (to-flash memory)
T2
NVM_13
I/O
NVMD_[15:0] multiplexed address/data (to-flash memory)
T3
NVM_12
I/O
NVMD_[15:0] multiplexed address/data (to-flash memory)
T4
NVM_11
I/O
NVMD_[15:0] multiplexed address/data (to-flash memory)
R1
NVM_10
I/O
NVMD_[15:0] multiplexed address/data (to-flash memory)
R2
NVM_9
I/O
NVMD_[15:0] multiplexed address/data (to-flash memory)
R3
NVM_8
I/O
NVMD_[15:0] multiplexed address/data (to-flash memory)
R4
NVM_7
I/O
NVMD_[15:0] multiplexed address/data (to-flash memory)
P1
NVM_6
I/O
NVMD_[15:0] multiplexed address/data (to-flash memory)
P2
NVM_5
I/O
NVMD_[15:0] multiplexed address/data (to-flash memory)
P3
NVM_4
I/O
NVMD_[15:0] multiplexed address/data (to-flash memory)
P4
NVM_3
I/O
NVMD_[15:0] multiplexed address/data (to-flash memory)
N1
NVM_2
I/O
NVMD_[15:0] multiplexed address/data (to-flash memory)
N2
NVM_1
I/O
NVMD_[15:0] multiplexed address/data (to-flash memory)
N3
NVM_0
I/O
NVMD_[15:0] multiplexed address/data (to-flash memory)
L2
NVMOE_N
O
Output enable (active low)
M3
NVMWE_N
O
Write enable (active low)
U2
ENVMALE
O
Address latch enable.
R7
REXT_LVDS
S
External Resistor (6.2K
Ω, 1%)
AC8
PORT_A_29
I
Port A data RGB or LVDS (TA1-)
AB8
PORT_A_28
I
Port A data RGB or LVDS (TA1+)
AC7
PORT_A_27
I
Port A data RGB or LVDS (TB1-)
AB7
PORT_A_26
I
Port A data RGB or LVDS (TB1+)
AC6
PORT_A_25
I
Port A data RGB or LVDS (TC1-)
AB6
PORT_A_24
I
Port A data RGB or LVDS (TC1+)
AC5
PORT_A_23
I
Port A data RGB or LVDS (CK1-)
AB5
PORT_A_22
I
Port A data RGB or LVDS (CK1+)
AA5
PORT_A_21
I
Port A data RGB or LVDS NC
Y5
PORT_A_20
I
Port A data RGB or LVDS NC
AC4
PORT_A_19
I
Port A data RGB or LVDS (TD1-)
AB4
PORT_A_18
I
Port A data RGB or LVDS (TD1+)
AC3
PORT_A_17
I
Port A data RGB or LVDS (TE1-)
AB3
PORT_A_16
I
Por A data RGB or LVDS (TE1+)
AC1
PORT_A_15
I
Port A data RGB or LVDS (TA2-)
AC2
PORT_A_14
I
Port A data RGB or LVDS (TA2+)
AB1
PORT_A_13
I
Port A data RGB or LVDS (TB2-)
AB2
PORT_A_12
I
Port A data RGB or LVDS (TB2+)
AA3
PORT_A_11
I
Port A data RGB or LVDS NC
AA4
PORT_A_10
I
Port A data RGB or LVDS NC
AA1
PORT_A_9
I
Port A data RGB or LVDS (TC2-)
AA2
PORT_A_8
I
Port A data RGB or LVDS (TC2+)
Y1
PORT_A_7
I
Port A data RGB or LVDS (CK2-)
Y2
PORT_A_6
I
Port A data RGB or LVDS (CK2+)
Wl
PORT_A_5
I
Port A data RGB or LVDS (TD2-)
W2
PORT_A_4
I
Port A data RGB or LVDS (TD2+)
V1
PORT_A_3
I
Port A data RGB or LVDS (TE2-)
V2
PORT_A_2
I
Port A data RGB or LVDS (TE2+)
V3
PORT_A_1
I
Port A data RGB or LVDS NC
V4
PORT_A_0
I
Port A data RGB or LVDS NC
W4
PORT_ A_PCS1
I/O
Port A panel control. NC
W3
PORT_A_PCS2
I
Port A panel control. HSYNC_OSC
Y4
PORT_A_PCS3
I
Port A panel control. VSYNC_OSC
Y3
PORT_A_PCS4
I/O
Port A panel control. NC
AA6
PORT_A_PCS5
I/O
Port A panel control. NC
Y7
PORT_A_PCS6
I/O
Port A panel control. NC
AA7
PORT_A_REV
I/O
Port A panel control. NC
Y6
PORT_A_CLK
I/O
Port A clock.
AB13
PORT_B_16
I/O
Port B data. NC
Y13
PORT_B_15
I/O
Port B data. NC
AA12
PORT_B_14
I/O
Port B data. NC
AC12
PORT_B_13
I/O
Port B data. NC
LC-42XD10E/RU
5 – 8
Y12
PORT_B_12
I/O
Port B data. NC
AB12
PORT_B_11
I/O
Port B data. NC
AA11
PORT_B_10
I/O
Port B data. NC
AC11
PORT_B_9
I/O
Port B data. NC
Y11
PORT_B_8
I/O
Port B data. NC
Y10
PORT_B_7
I/O
Port B data. NC
AB10
PORT_B_6
I/O
Port B data. NC
AA9
PORT_B_5
I/O
Port B data. NC
AC9
PORT_B_4
I/O
Port B data. NC
Y9
PORT_B_3
I/O
Port B data. NC
AB9
PORT_B_2
I/O
Port B data. NC
AA8
PORT_B_1
I/O
Port B data. NC
Y8
PORT_B_0
I/O
Port B data. NC
AC10
PORT_B_H
I/O
Port B H-Sync.
AB11
PORL_B_V
I/O
Port B V-Sync.
AA10
PORT_B_CLK
I/O
Port B clock.
AC15
PORT_C_9
I/O
Port C data . NC
AA15
PORT_C_8
I/O
Port C data. NC
AB15
PORT_C_7
I/O
Port C data. NC
Y15
PORT_C_6
I/O
Port C data. NC
AC14
PORT_C_5
I/O
Port C data. NC
AA14
PORT_C_4
I/O
Port C data. NC
AB14
PORT_C_3
I/O
Port C data. NC
Y14
PORT_C_2
I/O
Port C data. NC
AC13
PORT_C_1
I/O
Port C data. NC
AA13
PORT_C_0
I/O
Port C data. NC
Y16
PORT_C_H
I
Port C H-Sync.
AB16
PORT_C_V
I
Port C V-Sync.
AA16
PORT_C_CLK
I
Port C clock.
D11
PORT_D_23
I
Port D data. DINB[7] HDMI-B7
A12
PORT_D_22
I
Port D data. DINB[7] HDMI-B6
C11
PORT_D_21
I
Port D data. DINB[7] HDMI-B5
B11
PORT_D_20
I
Port D data. DINB[7] HDMI-B4
D10
PORT_D_19
I
Port D data. DINB[7] HDMI-B3
A11
PORT_D_18
I
Port D data. DINB[7] HDMI-B2
C10
PORT_D_17
I
Port D data. DINB[7] HDMI-B1
B10
PORT_D_16
I
Port D data. DINB[7] HDMI-B0
D13
PORT_D_15
I
Port D data. DINB[7] HDMI-G7
A14
PORT_D_14
I
Port D data. DINB[7] HDMI-G6
C13
PORT_D_13
I
Port D data. DINB[7] HDMI-G5
B13
PORT_D_12
I
Port D data. DINB[7] HDMI-G4
D12
PORT_D_11
I
Port D data. DINB[7] HDMI-G3
A13
PORT_D_10
I
Port D data. DINB[7] HDMI-G2
C12
PORT_D_9
I
Port D data. DINB[7] HDMI-G1
B12
PORT_D_8
I
Port D data. DINB[7] HDMI-G0
D15
PORT_D_7
I
Port D data. DINB[7] HDMI-R7
A16
PORT_D_6
I
Port D data. DINB[7] HDMI-R6
C15
PORT_D_5
I
Port D data. DINB[7] HDMI-R5
B15
PORT_D_4
I
Port D data. DINB[7] HDMI-R4
D14
PORT_D_3
I
Port D data. DINB[7] HDMI-R3
A15
PORT_D_2
I
Port D data. DINB[7] HDMI-R2
C14
PORT_D_1
I
Port D data. DINB[7] HDMI-R1
B14
PORT_D_0
I
Port D data. DINB[7] HDMI-R0
C16
PORT_D_DE
I
Port D DINEN data enable
D16
PORT_D_H
I
Port D H-sync.
A17
PORT_D_V
I
Port D V-sync.
B16
PORT_D_CLK
I
Port D clock.
T22
PORT_E_9
I/O
Port E data. NC
T20
PORT_E_8
I/O
Port E data. NC
U23
PORT_E_7
I/O
Port E data. NC
U21
PORT_E_6
I/O
Port E data. NC
U22
PORT_E_5
I/O
Port E data. NC
U20
PORT_E_4
I/O
Port E data. NC
V23
PORT_E_3
I/O
Port E data. NC
V21
PORT_E_2
I/O
Port E data. NC
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