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LC-42XD10E/RU

5 – 9

V22

PORT_E_1

I/O

Port E data.      NC

V20

PORT_E_0

I/O

Port E data.      NC

T21

PORT_E_CLK

I/O

Port E data.      NC

N20

PORT_F_9

O

Port F data.     FRCI_7   

P23

PORT_F_8

O

Port F data.     FRCI_6

P21

PORT_F_7

O

Port F data.     FRCI_5

P22

PORT_F_6

O

Port F data.     FRCI_4

P20

PORT_F_5

O

Port F data.     FRCI_3

R23

PORT_F_4

O

Port F data.     FRCI_2

R21

PORT_F_3

O

Port F data.     FRCI_1

R22

PORT_F_2

O

Port F data.     FRCI_0

R20

PORT_F_1

O

Port F data.     NC

T23

PORT_F_0

O

Port F data.     NC

N21

PORT_F_CLK

O

Port F clock.

G22

PORT_G_9

I

Port G data.     FRCO_7B 

H23

PORT_G_8

I

Port G data.     FRCO_6B

H21 

PORT_G_7

I

Port G data.     FRCO_5B

H22 

PORT_G_6 

I

Port G data.     FRCO_4B

H20 

PORT_G_5 

I

Port G data.     FRCO_3B

J23 

PORT_G_4

I

Port G data.     FRCO_2B

J21 

PORT_G_3

I

Port G data.     FRCO_1B

J22 

PORT_G_2 

I

Port G data.     FRCO_0B

J20 

PORT_G_1 

I

Port G data.     NC

K23 

PORT_G_0 

I

Port G data.     NC

G23 

PORT_G_CLK 

I

Port G clock.   

D19 

P29 

I

CPU I/O PORT   HDMI_INT          (from IC1905)

C19 

P28 

I

CPU I/O PORT   HOTP_CONT1    (to EXT5)

B19 

P27 

I

CPU I/O PORT   HOTP_CONT0    (to EXT5)

A19 

P26 

O

CPU I/O PORT   POWER_ERR      (to power-unit)

C20 

P25 

I

CPU I/O PORT   BL_ERR            (from INV)

B20 

P24 

I/O

CPU I/O PORT   DTM_IRQ          NC

A20 

P23 

I

CPU I/O PORT   CEC_IN            (to IC2701)

B21 

P22 

O

CPU I/O PORT   AVLINK,2_OUT  (from Q2702)

A21 

P21 

I

CPU I/O PORT   AVLINK2_IN      (to Q2711)

A22 

P20 

O

CPU I/O PORT   PCON2            (to power-unit)

A23 

P19 

O

CPU I/O PORT   PCON1            (to power-unit)

B22 

P18 

O

CPU I/O PORT   AVLINK1_OUT   (to Q***)

B23 

P17 

I

CPU I/O PORT   AVLINK1_IN      (from Q***)

C21 

P16 

O

CPU I/O PORT   FPGA_SDE       (to IC1710)

C22 

P15 

O

CPU I/O PORT   FPGA_SDA       (to IC1710)

C23 

P14 

O

CPU I/O PORT   FPGA_SCK       (to IC1710)

D20 

P13 

O

CPU I/O PORT   FPGA_SDA0      (to IC1710)

D21 

P12 

O

CPU I/O PORT   FAN_ERR         (to power-unit)

D22 

P11 

O

CPU I/O PORT   MUTE_SP         (to Q1101/2)

D23 

P10

O

CPU I/O PORT   SV1JSW          (IN3SW  to IC1201)

E20 

P9 

O

CPU I/O PORT   STBY_POW      (to key-unit)

E21 

P8 

O

CPU I/O PORT   CEC1_OUT      (from IC2701)

E22 

P7 

O

CPU I/O PORT   LED_POW_G     (to R/C-unit)

E23 

P6 

O

CPU I/O PORT   LED_POW_R     (to R/C-unit)

F20 

P5 

I

CPU I/O PORT   NVM_CE_N      (to IC3503)

F21 

P4 

O

CPU I/O PORT   HDMI_RESET   (to IC1905)

F22 

P3 

O

CPU I/O PORT   LCD_POW       (to power-unit)

F23 

P2 

I

CPU I/O PORT   RXD              (to RS232C-driver)

G20 

P1

O

CPU I/O PORT   TXD              (to RS232C-driver)

G21 

P0

O

CPU I/O PORT   IRIN              (to R/C-unit)

U12, U16 

VDDA18_ADC 

S

Analog  Supply power for ADC (1.8V)   

U14, T17 

VDDA33_ADC 

S

Analog  Supply power for ADC (3.3V)   

K17 

VDDA33_CADC 

S

Analog  Supply power for CADC (3.3V)  

N17 

VDD_PLL 

S

Analog  Supply power for PLL (1.8V)  

U7 

VDDPLLVDS 

S

Analog  Supply power for LVDSPLL (1.8V)  

M7, J7, U8, G12, G13, L17, 

M17 

VDDD 

S

Core supply power (3.3V)  

N7,U10, R17, G14 

VDDP 

S

Pad supply power (3.3V)   

G10, G11, K7, L7 

VDDPSD 

S

DRAM interface supply power (2.5V)   

P7, U9 

VDDLVDS 

S

LVDS supply power.   (3.3V)

U11, U15 

VSSA18_ADC 

S

Analog ground for ADC.   

LC-42XD10E/RU

5 – 10

U13, U17 

VSSA33_ADC 

S

Analog ground for ADC.   

J17 

VSSA33_CADC 

S

Analog ground for CADC.   

P17 

VSS_PLL 

S

Analog ground for PLL.   

N14, P10, P14, N14, M14, 

L14, K14, K13, T7 

VSS 

S

Core & pad supply ground.   

K10, L10, K12, K11, M10 

VSSPSD 

S

DRAM interface supply ground.   

W20 

NC 

-

Not connected.   

LC-42XD10E/RU

5 – 11

256Mb DDR SDRAM

Pin No.

Pin Name

I/O

Pin Function

45,46

CK, CK

I

Clock: CK and CK are differential clock inputs.
All address and control input signals are sampled on the positive edge of CK and negative edge of CK.
Output (read) data is referenced to both edges of CK.
Internal clock signals are derived from CK/CK.

44

CKE

I

Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, 
and device input buffers and output drivers.
Taking CKE Low provides PRECHARGE POWER DOWN and SELF REFRESH 
operction (all bank idle)
CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry.
CKE is asynchronous for SELF REFRESH exit, and for output disable.
CKE must be maintained high throughput READ and WRITE accesses.
Input buffers, excluding CK, CK and CKE are disabled during POWER-DOWN.
Input buffers, excluding CKE are disabled during SELF REFRESH. 
CKE is an SSTL_2 input, but will detect an LVCMOS Low level after Vdd is applied upon 
1st power up, After VREF has become stable during the power on and initialization 
sequence, it must be maintained for proper operation of the CKE receiver.
For proper SELF-REFRESH entry and exit, VREF must be maintained to this input.

24

CS

I

Chip Select: CS enables (registered LOW) and disables (registered HIGH) the command 
decoder.
All commands are masked when CS is registered HIGH.
CS provides for external bank selection on systems with multiple banks.
CS is considered part of the command code.

21-23

RAS, CAS, WE 

I

Command Inputs: RAS, CAS, and WE (along with CS) define the command being
 entered.

20,47

LDM,(UDM)

I

Input Data Mask: DM is an input mask signal for write data.
Input data is masked when DM is sampled HIGH along with that input data during a 
WRITE access.
DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ and DQS loading.
For the x16, LDM corresponds to the data on DQ0>D7; UDM corresponds to the 
data on DQ8>DQ15.
DM may be driven high, low, or floating during READs.

26,27

BA0, BA1

I

Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ,WRITE 
or PRECHARGE command is being applied.

28-32,

35-42

A [0: 12]

I

Address Inputs: Provide the row address for ACTIVE commands, and the column 
address and AUTO PRECHARGE bit for READ/WRITE commands, to select one 
location out of the memory array in the respective bank. 
A10 is sampled during a PRECHARGE command to determine whether the 
PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH).
If only one bank is to be procreated, the bank is selected by BA0, BA1. 
The address inputs also provide the op-code during a MODE REGISTER SET 
command. 
BA0 and BA1 define which mode register is loaded during the MODE REGISTER 
SET command (MRS or EMRS).

2,4,5,7,

8,10,

11,13,

54,56,
57,59,
60,62,

63,65

DQ

I/O

Data Input/Output: Data bus.

16,51

LDQS,(U)DQS

I/O

Data Strobe: Output with read data, input with write data. 
Edge-aligned with read data, centered in write data. 
Used to capture write data. 
For the x16, LDQS corresponds to the data on DQ0>D7; UDQS corresponds to
the data on DQ8>DQ15

14,17,
19,25,
43,50,

53,

NC

-

No Connect: No internal electrical connection is present.

3,9,15,

55,61

VDDQ

-

DQ Power Supply: +2.5V 

± 0.2V. (+2.6V ± 0.1V for DDR400)

6,12,

52,58,

64

VSSQ

-

DQ Ground.

1,18,33,

VDD

-

Power Supply: +2.5V 

± 0.2V. (+2.6V ± 0.1V for DDR400)

LC-42XD10E/RU

5 – 12

128Mb Flash Memory

34,48,

66

VSS

-

Ground.

49

VREF

I

SSTL_2 reference voltage.

Pin No.

Pin Name

I/O

Pin Function

I

2-12, 

15,  

18-26,
54, 31

A0-A22

I

23 Address lnputs.    

35,37,3
9,41,44

,46,48,

50

DQ0-DQ7

I/O

8 Data Inputs / Outputs.   

35-

42,44-

50

DQ8-DQ14

I/O

7 Data Inputs / Outputs.   

51

DQ15A-1

I

Data Input/Output or Address Input.

32

CE

I

Chip Enable. 

34

 OS

O

Output Enable.

13

WE

I

Write Enable. 

16

Vpp/WP

I

Hardware Vpp/ Write Protect 

14

RP

I

Reset/Block Temporary Unprotect.

17

R/B

O

Ready / Busy Output.    

53

BYTE

I

Byte/Word Organization Select.

43

VCC

-

Supply Voltage

33.52

VSS

-

Ground.    

27,28,5

5,56

NC

-

Not Connected Internally.    

29

VCCQ

-

Supply Voltage for Input/Output.