Sharp LC-42XD10E (serv.man5) Service Manual ▷ View online
LC-42XD10E/RU
5 – 17
40
RGBOUT3
O
Tristate (SELOMODE=0)
Digital (red: SELRB=0; blue: SELRB=1;)
Output (SELOMODE=1)
Digital (red: SELRB=0; blue: SELRB=1;)
Output (SELOMODE=1)
41
RGBOUT2
O
Tristate (SELOMODE=0)
Digital (red: SELRB=0; blue: SELRB=1;)
Output (SELOMODE=1)
Digital (red: SELRB=0; blue: SELRB=1;)
Output (SELOMODE=1)
42
RGBOUT1
O
Tristate (SELOMODE=0)
Digital (red: SELRB=0; blue: SELRB=1;)
Output (SELOMODE=1)
Digital (red: SELRB=0; blue: SELRB=1;)
Output (SELOMODE=1)
43
RGBOUT0
O
Tristate (SELOMODE=0)
Digital (red: SELRB=0; blue: SELRB=1;)
Output [LSB] (SELOMODE=1)
Digital (red: SELRB=0; blue: SELRB=1;)
Output [LSB] (SELOMODE=1)
44
YOUT9
O
Tristate (ENITUE=0)
Digital (luminance/green) output [MSB] (ENITUE=1)
Digital (luminance/green) output [MSB] (ENITUE=1)
45
YOUT8
O
Tristate (ENITUE=0)
Digital (luminance/green) output (ENITUE=1)
Digital (luminance/green) output (ENITUE=1)
46
YOUT7
O
Tristate (ENITUE=0)
Digital (luminance/green) output (ENITUE=1)
Digital (luminance/green) output (ENITUE=1)
47
VDDD2
S
Supply digital core (1.8 V)
48
VSSD2
S
Supply digital core (0 V)
49
VDDP3
S
Supply digital pad (3.3 V)
50
VSSP3
S
Supply digital pad (0 V)
51
NC
-
No Connection
52
YOUT6
O
Tristate (ENITUE=0)
Digital (luminance/green) output (ENITUE=1)
Digital (luminance/green) output (ENITUE=1)
53
YOUT5
O
Tristate (ENITUE=0)
Digital (luminance/green) output (ENITUE=1)
Digital (luminance/green) output (ENITUE=1)
54
VSSP4
S
Supply digital pad (0 V)
55
YOUT4
O
Tristate (ENITUE=0)
Digital (luminance/green) output (ENITUE=1)
Digital (luminance/green) output (ENITUE=1)
56
VDDP4
S
Supply digital pad (3.3 V)
57
YOUT3
O
Tristate (ENITUE=0)
Digital (luminance/green) output (ENITUE=1)
Digital (luminance/green) output (ENITUE=1)
58
YOUT2
O
Tristate (ENITUE=0)
Digital (luminance/green) output (ENITUE=1)
Digital (luminance/green) output (ENITUE=1)
59
YOUT1
O
Tristate (ENITUE=0)
Digital (luminance/green) output (ENITUE=1)
Digital (luminance/green) output (ENITUE=1)
60
YOUT0
O
Tristate (ENITUE=0)
Digital (luminance/green) output [LSB] (ENITUE=1)
Digital (luminance/green) output [LSB] (ENITUE=1)
61
CLKF20
O
Output clock 20.25 MHz disabled (CLKF20ON=0)
Output clock 20.25 MHz enabled (CLKF20ON=1)
Output clock 20.25 MHz enabled (CLKF20ON=1)
62
UVOUT9
O
Tristate (ENITUE=0)
Digital (chrominance/blue) output [MSB] (ENITUE=1and SELRB=0)
Digital (chrominance/red) output [MSB] (ENITUE=1and SELRB=1)
Digital (chrominance/blue) output [MSB] (ENITUE=1and SELRB=0)
Digital (chrominance/red) output [MSB] (ENITUE=1and SELRB=1)
63
VSSD30
S
Supply digital core (0 V)
64
VSSD31
S
Supply digital core (0 V)
65
VDDD30
S
Supply digital core (1.8 V)
66
VDDD31
S
Supply digital core (1.8 V)
67
UVOUT8
O
Tristate (ENITUE=0)
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
68
UVOUT7
O
Tristate (ENITUE=0)
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
69
VSSP50
S
Supply digital pad (0 V)
70
VSSP51
S
Supply digital pad (0 V)
71
VSSP52
S
Supply digital pad (0 V)
72
VDDP5
S
Supply digital pad (3.3 V)
73
UVOUT6
O
Tristate (ENITUE=0)
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
74
NC
-
No Connection
75
NC
-
No Connection
76
UVOUT5
O
Tristate (ENITUE=0)
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
77
NC
-
No Connection
LC-42XD10E/RU
5 – 18
78
UVOUT4/
INTR
INTR
O
Tristate (ENITUE=0)
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
Interrupt signal output from
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
Interrupt signal output from
µC (CPUIRQ=5)
Static 0 (CPUIRQ=6)
Static 1 (CPUIRQ=7)
Static 1 (CPUIRQ=7)
79
VDDP6
S
Supply digital pad (3.3 V)
80
VSSP6
S
Supply digital pad (0 V)
81
UVOUT3
O
Tristate (ENITUE=0)
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
82
UVOUT2
O
Tristate (ENITUE=0)
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
83
UVOUT1
O
Tristate (ENITUE=0)
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
84
UVOUT0
O
Tristate (ENITUE=0)
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
Digital (chrominance/blue) output (ENITUE=1 and SELRB=0)
Digital (chrominance/red) output (ENITUE=1 and SELRB=1)
85
VDDD4
S
Supply digital core (1.8 V)
86
VSSD4
S
Supply digital core (0 V)
87
VDDA0
S
Supply analog DAC SVM (3.3 V)
88
ASVMOUT
O
Middle level (STANDBY=1)
Analog SVM output (ACTFBL=0 and STANDBY=1)
Analog SVM output (control by SVMOFF possible)
(ACTFBL=1 and STANDBY=0)
Analog SVM output (ACTFBL=0 and STANDBY=1)
Analog SVM output (control by SVMOFF possible)
(ACTFBL=1 and STANDBY=0)
89
VSSA0
S
Supply analog DAC SVM (0 V)
90
VDDA1
S
Supply analog DAC B/U (3.3 V)
91
AUOUT
O
Middle level (STANDBY=0)
Chrominance output (STANBY=1)
Chrominance output (STANBY=1)
92
VSSA1
S
Supply analog DAC B/U (0 V)
93
VDDA2
S
Supply analog DAC G/Y (3.3 V)
94
AYOUT
O
Middle level (STANDBY=0)
Luminance output (STANDBY=1)
Luminance output (STANDBY=1)
95
VSSA2
S
Supply analog DAC G/Y (0 V)
96
VDDA3
S
Supply analog DAC R/V (3.3 V)
97
AVOUT
O
Middle level (STANDBY=0)
Chrominance output (STANDBY=1)
Chrominance output (STANDBY=1)
98
VSSA3
S
Supply analog DAC R/V (0 V)
99
VSSA4
S
Supply analog band gap (0 V)
100
VDDA4
S
Supply analog band gap (3.3 V)
101
VSSD5
S
Supply digital core (0 V)
102
VDDD5
S
Supply digital core (1.8 V)
103
NC
-
No Connection
104
NC
-
No Connection
105
SCL
I/O
I2C bus clock
106
SDA
I/O
I2C bus data
107
NC
-
No Connection
108
NC
-
No Connection
109
VSSP7
S
Supply digital pad (0 V)
110
VDDP7
S
Supply digital pad (3.3 V)
111
TMS
I
Test mode select (3.3 V)
112
NC
-
No Connection
113
TDO/
SVMOFF
SVMOFF
O/I
Test data out (ACTSVMOFF=1)
SVM input signal (ACTSVMOFF=0)
SVM input signal (ACTSVMOFF=0)
114
TDI
I
Test data in (0V)
115
TCLK
I
Test clock (3.3 V)
116
INTR
O
Interrupt signal
Static 0 (CPUIRQ2=00)
Static 1 (CPUIRQ2=01)
Interrupt signal output from
Static 0 (CPUIRQ2=00)
Static 1 (CPUIRQ2=01)
Interrupt signal output from
µC (CPUIRQ2= 1x)
117
656I02
I
Digital (luminance) input [LSB]
118
656I12
I
Digital (luminance) input
119
656I22
I
Digital (luminance) input
120
656I32
I
Digital (luminance) input
121
656I42
I
Digital (luminance) input
122
656I52
I
Digital (luminance) input
LC-42XD10E/RU
5 – 19
123
656I62
I
Digital (luminance) input
124
656I72
I
Digital (luminance) input
125
CLKIN2
I
Clock input [max. 81.0 MHz]
126
UVIN0
I
Digital (chrominance) input [LSB]
127
UVIN1
I
Digital (chrominance) input
128
UVIN2
I
Digital (chrominance) input
129
UVIN3
I
Digital (chrominance) input
130
VSSP8
S
Supply digital core (0 V)
131
VDDP8
S
Supply digital core (3.3 V)
132
VDD8M
S
Supply memory (1.8 V)
133
VSSD60
S
Supply digital core (0 V)
134
VSSD61
S
Supply digital core (0 V)
135
VDDD60
S
Supply digital core (1.8V)
136
VDDD61
S
Supply digital core (1.8 V)
137
UVIN4
I
Digital (chrominance) input
138
UVIN5
I
Digital (chrominance) input
139
UVIN6
I
Digital (chrominance) input
140
UVIN7
I
Digital (chrominance) input [MSB]
141
NC
-
No Connection
142
656I0/YIN0
I
Digital (luminance) input [LSB]
143
VSSP9
S
Supply digital pad (0 V)
144
VDDP9
S
Supply digital pad (3.3 V)
LC-42XD10E/RU
5 – 20
9. IC1710: RH-IXB946WJZZ
FPGA
Pin No.
Pin Name
I/O
Pin Function
Sheet name
1
EXP[8]
O
REG2 light control system identify
REG2
2
EXP[9]
O
REG external sync identify
REG
3
EXP[10]
O
QS parameter
TEMP3
4
EXP[11]
O
QS parameter
TEMP2
5
EXP[12]
O
QS parameter
TEMP1
6
EXP[13]
O
QS parameter
QSSET
7
EXP[14]
O
LED SLEEP (ON at "L")
LEDSLP
8
EXP[15]
O
LED OPC (ON at "L")
LEDOPC
9
VCCIO1 3.3V
-
Power supply 3.3V
3.3V
10
GND
-
Ground
GND
11
GND
-
Ground
GND
12
PCLK
I
Panel clock 74.25MHz
PCLK
13
VCCINT 3.3V
-
Power supply 3.3V
3.3V
14
I/O
-
GND*
NC
15
I/O
-
GND*
NC
16
I/O
-
GND*
NC
17
OSCOUT
O
Light control clock output (No lamp light-up at initial “L”)
OSCOUT
18
I/O
-
GND*
NC
19
OFLOUT
O
Light control PWM output (No lamp light-up at initial “L”)
OFL1OUT
20
OFL2OUT
O
Light control PWM output
OFL2OUT
21
I/O
-
GND*
NC
22
(TMS)
I
Inline Program JTAG TMS/ OPEN
TMS
23
(TDI)
I
Inline Program JTAG DataIn/ OPEN
TDI
24
(TCK)
I
Inline Program JTAG Clock/ OPEN
TCK
25
(TDO)
O
Inline Program JTAG DataOut/ OPEN
TDO
26
I/O
O
Write mode Vpp-cont
NC
27
I/O
-
GND*
NC
28
I/O
-
GND*
NC
29
I/O
-
GND*
NC
30
I/O
-
GND*
NC
31
VCCIO1 3.3V
-
Power supply 3.3V
3.3V
32
GND
-
Ground
GND
33
I/O
-
GND*
NC
34
EXP[16]
O
MSP FRC Reset Note 2
RESET_A
35
EXP[17]
O
DTU-CVBS/ (S-VY
⋅CVBS) switching
G_ONSYNC
36
EXP[18]
O
DTV/PC/HDMI switching
DTVPC
37
EXP[19]
O
DTV/PC/HDMI switching
DTVHDMI
38
EXP[20]
O
E2PROM WP for HDMI
HDMI_WP
39
EXP[21]
O
Panel flip horizontal
LCDLR
40
EXP[22]
O
Panel flip vertical
LCDUD
41
EXP[23]
O
Panel 50/60Hz
FRAME
42
I/O
-
GND*
NC
43
I/O
-
GND*
NC
44
I/O
-
GND*
NC
45
VCCIO1 3.3V
-
Power supply 3.3V
3.3V
46
GND
-
Ground
GND
47
EXP[24]
O
Common Bias Adjustment write Protect.
TCON_WP
48
EXP[25]
O
Not used
NC
49
EXP[26]
O
Chage shear impulse on/off.
CSI
50
EXP[27]
O
S+8V Control Signal
S+8V-CTL
51
EXP[28]
O
Memory Bank Select.
BANK
52
EXP[29]
O
Not used
NC
53
EXP[30]
O
Not used
NC
54
EXP[31]
O
Not used
NC
55
I/O
-
GND*
NC
56
-
GND*
NC
57
I/O
-
GND*
NC
58
I/O
-
GND*
NC
59
VCCIO2 3.3V
-
Power supply 3.3V
3.3V
60
GND
-
Ground
GND
61
I/O
-
GND*
NC
62
GCLR
I
VGC_Reset_Line
RESET_N
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