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LC-42XD10E/RU

5 – 21

63

VCCINT 3.3V

-

Power supply 3.3V

3.3V

64

SCK

I

from VGC

SCK

65

GND

-

Ground

GND

66

SEN

I

from VGC

FPGA_SDE

67

SDAI

I

from VGC

FPGA_SDA

68

I/O

-

GND*

NC

69

SDAO

O

Write mode RESET output

FPGA_SDAO

70

I/O

-

GND*

NC

71

I/O

-

GND*

NC

72

I/O

-

GND*

NC

73

I/O

-

GND*

NC

74

I/O

-

GND*

NC

75

OFL2EN

I

OFL2_EN external setting terminal

GND

76

I/O

-

GND*

NC

77

I/O

O

VGC write Open drain (Write mode at "H")

BOOT

78

I/O

-

GND*

NC

79

GND

-

Ground

GND

80

VCCIO2 3.3V

-

Power supply 3.3V

3.3V

81

I/O

I

VSYNC_OSC

VSYNC

82

I/O

I

HSYNC_OSC

HSYNC

83

I/O

-

GND*

NC

84

I/O

-

GND*

NC

85

EXP[0]

O

DTI2CSEL

DTI2CSEL

86

EXP[1]

O

DTM_RESET

DTM_RESET

87

EXP[2]

O

DTU_ON (Analog tuner at "L" D-tuner at "H")

DTU_ON

88

EXP[3]

O

232C on/off SW (RS232C action at "H": VGC write enabled)

IREM_SW

89

EXP[4]

O

STB (LAMP ON)

STB

90

EXP[5]

O

S2_MUTE

S2MUTE

91

EXP[6]

O

ANT+5V ON

ANT+5V ON

92

EXP[7]

O

S_MUTE

S-MUTE

93

GND

-

Ground

GND

94

VCCIO2 3.3V

-

Power supply 3.3V

3.3V

95

I/O

-

GND*

NC

96

I/O

-

GND*

NC

97

I/O

-

GND*

NC

98

I/O

-

GND*

TP1703

99

I/O

-

GND*

NC

100

OFL-SET-IN

I

OFLWD[8] external setting terminal

GND

GND*: Non-configured pins are fixed at GND.
Terminals' electrical characteristics are referred to in the EPM240T100C5N data sheet of Altera.

Note 1: Reset output monitor terminal with EXP31 in use.
Note 2: Composed of GCLR and OR.

LC-42XD10E/RU

5 – 22

Step Down Converter.

Step Down Converter

Pin No.

Pin Name

I/O

Pin Function

1

BS

I

High-Side Gate Drive Boost input.
BS supplies the drive for the high-side n-channel MOSFET switch.
Connect a 10nF or greater capacitor from SW to BS to power the high-side switch.

2

IN

I

Power input.
IN supplies the power to the IC, as well as the step-down converter switches.
Drive IN with a 4.75V to 15V power source.
Bypass IN to GND with a suitably large capacitor to eliminate noise on the input to the IC.
See input Capacitor.

3

SW

O

Power Switching Output. 
SW is the switching node that supplies power to the output.
Connect the output LC filter from SW to the output load.
Note that a capacitor is required from SW to BS to power the high-side switch.

4

GND

-

Ground.

5

FB

I

Feedback input.
FB senses the output voltage to regulate that voltage.
Drive FB with a resistive voltage divider from the output voltage. 
The feedback threshold is 1.22V.
See Setting the Output Voltage.

6

COMP

-

Compensation Node.
COMP is used to compensate the regulation control loop.
Connect a series RC network from COMP to GND to compensate the regulation control loop.
See Compensation.

7

EN

I

Enable input.
EN is a digital input that turns the regulator on or off.
Drive EN high to turn on the regulator, drive it low to turn it off.
For automatic startup, leave EN unconnected.

8

N/C

-

No Connect.

Pin No.

Pin Name

I/O

Pin Function

1

BS

I

High-Side Gate Drive Boost lnput.
BS supplies the drive for the high-side n-channel MOSFET Switch.
Connect a 4.7nF or greater capacitor from SW to BS to power the high side switch.         

2

IN

I

Power input.
IN supplies the power to the IC, as well as the step-down converter switches.
Drive IN with a 4.75V to 23V power  source.
Bypass IN to GND with a suitably  large capacitor to eliminate noise on the input to the IC.
See Input Capacitor.        

3

SW

O

Power Switching Output.
SW is the switching node that supplies power to the output.
Connect the output LC filter from SW to the output load.
Note that a capacitor is required from SW to BS to power the high-side switch.        

4

GND

-

Ground. (Note: Connect the exposed pad on backside to Pin4).         

5

FB

I

Feedback input.
FB senses the output voltage to regulate that voltage.
Drive FB with a resistive voltage divider from the output voltage.
The feedback threshold is 1.222V.
See  Setting the Output Voltage.     

6

COMP

I

Compensation Node.
COMP is used to compensate the regulation control loop.
Connect a series RC network from COMP to GND to compensate the regulation control loop.
In same cases,  an additional capacitor from COMP to GND is required.
See Compensation.        

7

EN

I

Enable input 
EN is a digital input that turns the regulator on or off.
Drive EN high to turn on the regulator, drive it low to tum it off.
For automatic startup, leave EN unconnected.        

8

SS

I

Soft Start Control input.
SS controls the soft start period.
Connect a capacitor from SS to GND to set the soft-start period.
A 0.1

µF capacitor sets the soft-start period to l0ms

To disable the soft-start featur CIeave SS unconnected.       

LC-42XD10E/RU

5 – 23

SOUND AMP

DIGITAL-PROCESSOR

Pin No.

Pin Name

I/O

Pin Function

1

VSSD

-

negative digital supply voltage; heat spreader

2

VSSA

-

Negative analogue supply voltage.

3

INN

I

inverting input.

4

INP

I

non inverting input.

5

VDDA

-

positive analog supply voltage.

6

POWERUP

I

power-up input.

7

ENABLE

I

enable input.

8

DIAG

O

diagnostic output.

9

CGND

-

control ground; reference ground for pins POWERUP, ENABLE and DIAG.

10

VSSD

-

negative digital supply voltage; heat spreader.

11

VSSD

-

negative digital supply voltage; heat spreader.

12

OVP

I

overvoltage protection reference input.

13

HVP

O

half supply voltage output for charging SE capacitor.

14

STABI

I

decoupling of internal stabilizer.

15

VSSP

-

negative power supply voltage.

16

OUT

O

PWM output.

17

BOOT

I

bootstrap capacitor connection.

18

VDDP

-

positive power supply voltage.

19

HVPI

I

half supply voltage output for reference voltage of input circuitry.

20

VSSD

-

negative digital supply voltage; heat spreader.

Pin No.

Pin Name

I/O

Pin Function

NET 
NAME

A8,B8,B19,B20,C8,
D8,F1-F4,U23,U24,
V1-V4,AA23-AA26,
AC7,AC15,AD7,    
AD15,AE7,AE15,AF7,AF15

VDD

-

1.8 V power supply

P1.8V

B22,C3,C4,C10,D3,D4,D10,
E4,G25,M1-
M4,W23,W24,AC3,AC4,AC1
0,AC13,AC19,AC23,AC24,A
D3,AD4,AD10,AD13,AD19,A
D23, AD24

VDD3

-

3.3 V power supply

P3.3V

AD6

RTCVDD

-

Low power controller 1.8 V power supply

P1.8V

B13,B21,D25,K10-K17,L10-
L17,M10-M17,N10-
N17,P10-P17,R10-R17,T10-
T17,U10-U17

GND

-

Ground for power supplies

GND

C4

Others

Typical load, but the maximum is 75 pF.

S8

SDRAM/EMI

Typical load, but the maximum is 75 pF.

S8b

SDRAM/EMI

Typical load, but the maximum is 75 pF.

E8

EMI (programmable)

Typical load, but the maximum is 75 pF.

P4

PIO

Typical load, but the maximum is 75 pF.

AE11

VDDVDACRGB

-

3.3 V power supply for RGB video DAC

VDDDAC

AE9

VDDVDACYCC

-

3.3 V power supply for YCC video DAC

VDDDAC

AD11

GNDVDACRGB

-

Ground for RGB video DAC

GNDDAC

AD9

GNDVDACYCC

-

Ground for YCC video DAC

GNDDAC

AD8

SHIELDVDAC

-

Shield ground for 2 x video DACs

GND A

AE10

IREFDACRGB

-

RGB video DAC current reference

YOUT

AE8

IREFDACYCC

-

YCC video DAC current reference

AC9

VREFDACRGB

-

RGB video DAC voltage reference

AC8

VREFDACYCC

-

YCC video DAC voltage reference

A10

VDDVPLL

-

3.3 V power for video PLL

VDDPLL

C13

VDDAUDIOFSYN

-

1.8 V dedicated power for low jitter audio clock frequency synthe-
sizer

VDDF3

B12

GNDAUDIOFSYN

-

Dedicated ground for low jitter audio clock frequency synthesizer

GNDF3

C12

VDDGENFSYN

-

1.8 V dedicated power for nonaudio clock frequency synthesizer

VDDF3

B11

GNDGENFSYN

-

Dedicated ground for nonaudio clock frequency synthesizer

GNDF3

LC-42XD10E/RU

5 – 24

AA4

VDDAADAC

-

3.3 V power for audio DAC

VDDADC
A

AA2

VSSAADAC

-

Ground for audio DAC command switches

GNDA-
DAC

Y4

VDDASADAC

-

3.3 V power for audio DAC substrate

VDDA-
DAC

AB2

VCCAADAC

-

3.3 V power for audio DAC command switches

VDDA

AB3

GNDAADAC

-

Ground for audio DAC

GNDA-
DAC

AC2

VCCASADAC

-

3.3 V power for audio DAC command switches
substrate

VDDA

AD2

IREF

I

Audio DAC output reference current

AE2

VBGFIL

I

Audio DAC filtered output reference voltage

VBGFIL

AF4

LPCLKIN

I

Low power clock input (1.8 V tolerant)

CLOCK 
IN

AF5

LPCLKOSC

I/O

Low power clock oscillator (1.8 V tolerant)

CLOCK

A16

NO32XTAL1

I

Select for 32 kHz clock source 
 0: XTAL,      1: Internal divider

TCK

A13

CLK27MA

I

Selectable input clock to PLL or for x1 mode (5 V tolerant)

CLK27MH
Z

A11

CLKSPEEDSEL

I

PLL speed select (5 V tolerant)

A12

AUXCLKOUT

O

Auxiliary clock for general use (5 V tolerant)

AF6

notRESET

I

System reset (1.8 V tolerant)

SYSRE-
SET

AD14

notWDOGRSTOUT

O

Internal watchdog timer reset (5 V tolerant)

AE14

TDI

I

Boundary scan test data input (5 V tolerant)

TDI

AC14

TMS

I

Boundary scan test mode select (5 V tolerant)

TMS

AF16

TCK

I

Boundary scan test clock (5 V tolerant)

TCK

AF14

notTRST

I

Boundary scan test logic reset (5 V tolerant)

NOT-
TRST

AE13

TDO

O

Boundary scan test data output (5 V tolerant)

TDO

P1

DCUTRIGGERIN

I

External trigger input to DCU (5 V tolerant)

TRIGIN

P3

DCUTRIGGEROUT

O

Signal to trigger external debug circuitry (5 V tolerant)

TRIGOUT

C23

TSIN2LBYTECLK

I/O

Transport stream bit clock (5 V tolerant)

TS2CLK

C22

TSIN2LBYTECLKVA
LID

I/O

Transport stream bit clock valid edge (5 V tolerant)

TS2VAL

B23

TSIN2LERROR

I/O

Transport stream packet error (5 V tolerant)

D19

TSIN2LPACKETCLK

I/O

Transport stream packet strobe (5 V tolerant)

TS2STRT

B18,C18,D18,C19,C20,D20,
C21,D21

TSIN2LDATA[7:0]

I/O

Transport stream data (5 V tolerant)

TS2D[7:0]

P23

TSIN1BYTECLK

I

Transport stream bit/byte clock (5 V tolerant)

FECLK

M24

TSIN1BYTECLKVALI
D

I

Transport stream bit/byte clock valid edge (5 V tolerant)

FEVALID

M26

TSIN1ERROR

I

Transport stream packet error (5 V tolerant)

FEER-
ROR

N26

TSIN1PACKETCLK

I

Transport stream packet strobe (5 V tolerant)

FES-
TROUT

K26,J25,H24,J24,L26,L25,L
24,M23

TSIN1DATA[7:0]

I

Transport stream data in (5 V tolerant)

FED[7:0]

L3

notEMIRAS or
notCI_IORD1

O

Row address strobe for SDRAM

EMIRAS

K1

not_EMICAS or
not_CI_IOW1

O

Column address strobe for SDRAM

EMICAS

J1

notEMICSA

O

Peripheral chip select A

EMICSO

K3

notEMICSB

O

Peripheral chip select B

K2

notEMICSC

O

Peripheral chip select C

N4

notEMICSD

O

Peripheral chip select D

EMICS3

J2

notEMICSE

O

Peripheral chip select E

L2

notEMICSF

O

Peripheral chip select F

EMICS5

L1, N3

notEMIBE[1:0]

O

External device data bus byte enable. 1 bit per byte of the data bus.

EMIBE1,
EMIRAS

N1

notEMIOE or
not_CI_OE

O

External device output enable.

EMIOE

N2

notEMILBA or
notCI_Wea

O

Flash device load burst address.

EMILBA

P4

EMIWAITnot-
TREADY

I

External memory device target ready indicator (5 V tolerant)

CPUWAIT