Sharp LC-37AD1E (serv.man10) Service Manual ▷ View online
53
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LC-37AD1E
Ë
VHITC90A69F-1Y(ASSY:IC401)
3LINE DIGITAL COMB FILTER(NTSC/PAL)
»
Block Diagram
»
Pin Function
Pin No
.
P
in Name
I/O
Pin Function
1
BIAS
—
Bias for ADC
2
VRT
—
D range upper bias for ADC
3
VDD1
—
Power supply for ADC and DAC (analog system)
4
TESTI1
I
Test input
5
VSS2
—
GND for ADC (analog system)
6
VRB
—
D range lower bias for ADC
7
YCIN
I
Picture signal input
8
TEST
O
Reset control and TEST control at the time of shipment
9
K
ILLER
I
Y/C separation and vertical enhancer-off control
10
TESTI2
I
Test input
11
VDD3
—
Power supply for logic (digital system)
12
VSS3
—
GND for Logic and DRAM (digital system)
13
VDD2
—
Power supply for DRAM (digital system)
14
TESTI3
I
Test input
15
SCL
I
Clock input of IIC BUS
16
SDA
I
Data input of IIC BUS
17
MODE1
O
MODE1 output
18
TESTOUT
I
Test input
19
FSC
I
C
lock input
20
VDD4
—
Power supply for PLL (analog system)
21
VSS4
—
GND for PLL (analog system)
22
FIL
I
VCO control
23
PD
O
PLL detection output
24
VB2
—
Bias 2 for DAC
25
YOUT
O
Luminosity signal output
26
VSS1
—
GND for DAC (analog system)
27
COUT
O
Color signal output
28
VB1
—
Bias 1 for DAC
54
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LC-37AD1E
Ë
VHITA1318AF1EY (ASSY:IC604)
Synchronous processing for TV component signals, frequency measurement
»
Block Diagram
Pin No
.
P
in Name
I/O
Pin Function
»
Pin Function
1
H
D2-IN
I
Input the horizontal synchronizing signal.
It's polarity corresponds to both positive and negative.
Input from this pin does not be synchronized internally.
2
VD2-IN
I
Input the vertical synchronizing signal.
It's polarity corresponds to both positive and negative.
Input from this pin does not be synchronized internally.
3
HD1-IN
I
Input the horizontal synchronizing signal.
It's polarity corresponds to both positive and negative.
Input from this pin does not be synchronized internally.
4
VD1-IN
I
Input the vertical synchronizing signal.
It's polarity corresponds to both positive and negative.
Input from this pin does not be synchronized internally.
5
A
NALOG GND
—
The GND pin for analog circuit block.
6N
.C
—
It is a blank terminal. Please connect with GND.
7
AFC FILTER
—
Connect the filter for horizontal AFC. The frequency of the horizontal output is
varied by the volyage at this pin.
8N
.C
—
It is a blank terminal. Please connect with GND.
9
HVCO
—
Connect the ceramic oscillator for horizontal oscillator.
10
N.C
—
It is a blank terminal. Please connect with GND.
11
VCC
—
The VCC pin.(9.0V)
12
DAC2(H/C.
O
DAC2 output pin. When TEST mode, HD or composite sync signal to frequency
SYNC output)
counter circuit is output.
13
VD3-IN
I
Input the vertical synchronizing signal.
It's polarity corresponds to both positive and negative.
14
HD3-IN
I
Input the horizontal synchronizing signal.
It's polarity corresponds to both positive and negative.
15
CP-OUT
O
C
lamp pulse output pin. CP according to the incoming signal by which
synchronous reproduction is carried out is outputted.
16
HD1-OUT
O
HD output pin. This pin is open-collector system.
HD1/HD2 input signal is outputted from this terminal, without carrying out
synchronous processing.
It's polarity is switched by BUS write function.
17
N.C
—
It is a blank terminal. Please connect with GND.
18
DIGITAL GND
—
The GND pin for digital circuit block.
19
HD2-OUT
O
HD output pin. This pin is open-collector system.
HD1/HD2 input signal is outputted from this terminal, without carrying out
synchronous processing.
It's polarity is switched by BUS write function.
20
N.C
—
It is a blank terminal. Please connect with GND.
21
SDA
I/O
The SDA pin for I2C BUS.
22
SCL
I
The SCL pin for I2C BUS.
23
ADDRESS SW
I
S
lave address switch.
24
SYNC2-IN
I
It is the input of a synchronous separation circuit.
Y signal is inputted through a clamp capacitor.
25
DAC1(V. SYNC
O
DAC1 output pin. When TEST mode, VD or vertical sync signal to frequency
output)
counter circuit is output.
26
SYNC1-IN
I
It is the input of a synchronous separation circuit.
Y signal is inputted through a clamp capacitor.
27
N.C
—
It is a blank terminal. Please connect with GND.
28
VD1-OUT
O
VD output pin. This pin is open-collector system.
VD1/VD2 does not be synchronizing and they are output from this pin.
It's polarity is switched by BUS write function.
29
VD2-OUT
O
VD output pin. This pin is open-collector system.
VD1/VD2 does not be synchronizing and they are output from this pin.
It's polarity is switched by BUS write function.
30
DAC3
O
DAC2 output terminal. This pin is open-collector system. The pulse signal for a
shipment test is outputted at the time of TEST mode.
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LC-37AD1E
Ë
VHITB1274AF1EQ (ASSY:IC801)
VIDEO/CHROMA/SYNC. processor
»
Block Diagram
»
Pin Function
Pin No
.
P
in Name
I/O
Pin Function
1
CVBS1/Y1-IN
I
CVBS1 or a Y1-IN signal is inputted.
2
SYNC-IN
I
Synchronized signal is inputted.
3
CVBS-OUT
O
O
utput terminal of CVBS or a Y+C signal.
4
V
S
O
Counted-down vertical synchronized signal is outputted.
5
COMB Y-IN
I
Y
-signal outputted from comb-filter is inputted.
It opens, when not using it.
6
D-VDD
—
Power supply of a DDS/BUS/V-CD/H-CD block is supplied.
DC5V (standard)"
7
COMB C-IN
I
C-signal outputted from comb-filter is inputted.
It opens, when not using it."
8
D
-GND
—
GND terminal of a DDS/BUS/V-CD/H-CD block.
9
H
S
O
Horizontal synchronized signal which required H-AFC is outputted.
10
SCP
O
Sand Castle Pulse is outputted. A clamp pulse and a horizontal Blanking pulse
are outputted.
11
Yvi-IN
O
Y
-signal for a synchronous input selected by Video-SW is outputted.
12
SYNC-VCC
—
Power supply of a SYNC/HVCO block is supplied.
DC5V (standard)
13
SCL
I
SCL terminal of I2CBUS.
14
SDA
I/O
SDA terminal of I2CBUS.
15
YS3(RGB1-in)
I
S
electe SW of a main signal and RGB1 input signal.
Only when "RGB1-ENB" is set as "enable" by bus setup, the input of YS3
becomes effective.
16
SYNC-GND
—
GND terminal of a SYNC/HVCO block.
17
Cr1-IN
I
Y1-/Cb1/Cr1 signal is inputted.
18
Cb1-IN
I
19
Y1-IN
I
20
CLP-FIL
—
Filter for Y clamp is connected.
21
Y-OUT
O
Y/Cb/Cr signal is outputted.
22
Cb-OUT
O
23
Cr-OUT
O
24
YS1(YVbC2-IN)
I
Selecte SW of a main signal and YCrCb2 input signal.
25
B1-IN
I
RGB1 signal is inputted. This input is selected in YS3 or I2CBUS.
26
G1-IN
I
27
R1-IN
I
28
Y/C-GND
—
GND terminal of Y/C/Text/Video-SW / 1HDL block.
29
Cr2-IN
I
Y2/Cb2/Cr2 signal is inputted. This input is selected in YS1.
It opens, when not using it.
30
Cb2-IN
I
31
Y2-IN
I
32
Y/C-VCC
—
Power supply of Y/C/Text/Video-SW / 1HDL block is supplied.
DC5V (standard)
33
B2-IN
I
RGB2 signal is inputted. This input is selected in YS2.
It opens, when not using it.
34
G2-IN
I
35
R2-IN
I
36
YS2/YM(RGB2-IN)
I
S
electe SW of a main signal and RGB2 input signal.
37
FIL.
—
Connects with a Y/C-VCC terminal.
38
X'TAL
—
16.2MHz X'tal oscillation element is connected.
39
C3-IN
I
Chrominance signal is inputted. It opens, when not using it.
40
APC-FIL
—
Filter for a chrominance demodulater is connected.
41
CVBS3/Y3-IN
I
CVBS3 or Y3 signal is inputted. It opens, when not using it.
42
ADDRESS
I
S
lave address is set up.
43
C2-IN
I
Chrominance signal is inputted. It opens, when not using it.
44
CVBS2/Y2-IN
I
CVBS2 or Y2 signal is inputted. It opens, when not using it.
45
COMB SYS
O
The distinction result of the received color system is outputted from this terminal
and a terminal 46.
46
Fsc-OUT
O
Subcarrier is outputted.
47
AFC-FIL
—
Filter for AFC detection is connected.
48
C1-IN
I
Chrominance signal is inputted. It opens, when not using it.
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LC-37AD1E
»
Pin Function
Pin No
.
P
in Name
I/O
Pin Function
1
IN2-H
I
IN2-H:FIndependent H-synchronization signal input terminal
2
IN2-V
I
IN2-V:FIndependent V-synchronization signal input terminal
3
IN2-1
I
Signal input terminal of IN2 system
4
IN2-2
I
5
IN2-3
I
6
V
cc-MAT
—
Power supply terminal of a selector system and a synchronous processing
system
7
IN3-H
I
IN3-H:FIndependent H-synchronization signal input terminal
8
IN3-V
I
IN3-V:FIndependent V-synchronization signal input terminal
9
IN3-1
I
Signal input terminal of IN3 system
10
IN3-2
I
11
IN3-3
I
12
GND-MAT
—
Ground terminal of a selector system and a synchronous processing system
13
IN4-H
I
IN4-H:FIndependent H-synchronization signal input terminal
14
IN4-V
I
IN4-V:FIndependent V-synchronization signal input terminal
15
IN4-1
I
Signal input terminal of IN4 system
16
IN4-2
I
17
IN4-3
I
18
V-PH
—
Capacitor connection terminal for carrying out the peak hold of the V-sync.
19
IN5-H
I
IN5-H
Å
FIndependent H-synchronization signal input terminal
20
IN5-V
I
IN5-V
Å
FIndependent V-synchronization signal input terminal
21
IN5-1
I
Signal input terminal of IN5 system
22
IN5-2
I
23
IN5-3
I
24
H-PH
—
Capacitor connection terminal for carrying out the peak hold of the H-sync.
25
YG-OUT
O
Composite Video signal output terminal for synchronous separation.
26
YG-IN
I
Composite Video signal input terminal for synchronous separation.
27
IREF-SYNC
—
Reference current setting terminal (about 4.6 V)
28
VS-OUT
O
HV of IN1 system or HV of IN2 to IN5 system selector output, and this either are
chosen by I2 C BUS"YCBCR/MAT", and it outputs by positive.
29
HS-OUT
O
30
Vcc-OUT
O
P
ower supply terminal of RGB system
31
SCP-IN
I
Input terminal of Sand-Castle-Pulse
32
VTIM-IN
I
Input terminal of V-timing pulse.
33
HP-IN
I
Input terminal of H-pulse
34
GND-OUT
O
G
round terminal of RGB system
35
R-OUT
O
O
utput terminal of RGB signal
37
G-OUT
O
Outputted by 2.6 Vp-p at the time of the input of the white of 100IRE.
39
B-OUT
O
36
R-SH
—
Sample & Hold terminal for AKB of RGB
38
G-SH
—
40
B-SH
—
41
IK-IN
I
Reference pulse is returned to this terminal.
42
PABL-FIL
I
Peak hold terminal of Peak ABL.
43
ABL-FIL
I
LPF is formed to an ABL control signal.
44
ABL-IN
I
ABL control signal input terminal
45
YS/YM-1
I
Control input terminal of YM1/YS1
Input level corresponds with three values.
When the value of YM and each YS reaches, it serves also as the function
which turns off VM.
46
LR1-IN
I
S
ignal input terminal of analog RGB1
47
LG1-IN
I
48
LB1-IN
I
49
YS/YM-2
I
Control input terminal of YM2/YS2
Input level corresponds with three values.
When the value of YM and each YS reaches, it serves also as the function
which turns off VM.
50
LR2-IN
I
S
ignal input terminal of analog RGB2
51
LG2-IN
I
52
LB2-IN
I
53
ADDRESS
I
S
lave address setting terminal of I2C BUS.
54
DPIC-C
—
Capacitor is connected to black detection of dynamic picture (black extension)
at GND.
55
SCL
I
Input terminal of SCL(Serial Clock) of a I2C BUS standard.
56
SDA
I
Input terminal of SDA(Serial Data) of a I2C BUS standard.
57
DPIC-MUTE
I
MUTE of dynamic picture (black extension) is controllable with a terminal.
58
CLP-C
C
onnection terminal of the capacitor for Y-system clamp.
Ë
VHICXA2101Q-1Q(ASSY:IC803)
Multi Component Processor
»
Block Diagram
