Sharp LC-37AD1E (serv.man10) Service Manual ▷ View online
64
64-1
64-2
LC-37AD1E
Ë
RH-IXA416WJZZQ (ASSY:IC2501)
Multi Standard Sound Processor
»
Block Diagram
Pin No
.
Pin Name
I/O
Pin Function
»
Pin Function
1N
C
—
Not connected
2
I2C_CL
I/O
I2C clock
3
I2C_DA
I/O
I2C data
4
I2S_CL
I/O
I2S clock
5
I2S_WS
I/O
I2S word strobe
6
I2S_DA_OUT
O
I2S data output
7
I2S_DA_IN1
I
I2S1 data input
8
ADR_DA
O
ADR data output
9
ADR_WS
O
ADR word strobe
10
ADR_CL
O
ADR clock
11,12,13
DVSUP
—
Digital power supply 5V
14,15,16
DVSS
—
Digital ground
17
I2S_DA_IN2
I
I2S2-data input
18
NC
—
Not connected
19
I2S_CL3
I
I2S3 clock
20
I2S_WS3
I
I2S3 word strobs
21
RESETQ
I
Power-on-reset
22
I2S_DA_IN3
I
I2S3-data input
23
NC
—
Not connected
24
DACA_R
O
Headphone out, right
25
DACA_L
O
Headphone out, left
26
VREF2
—
Reference ground 2
27
DACM_R
O
Loudspeaker out, right
28
DACM_L
O
Loudspeaker out, left
29,31,32
NC
—
Not connected
30
DACM_SUB
O
Sub woofer output
33
SC2_OUT_R
O
SCART 2 output, right
34
SC2_OUT_L
O
SCART 2 output, left
35
VREF1
—
Reference ground 1
36
SC1_OUT_R
O
SCART 1 output, right
37
SC1_OUT_L
O
SCART 1 output, left
38
CAPL_A
—
Volume capacitor AUX
39
AHVSUP
—
Analog power supply 8V
40
CAPL_M
—
Volume capacitor MAIN
41,42
NC
—
Not connected
43,44
AHVSS
—
Analog ground
45
AGNDC
—
Analog reference voltage
46
NC
—
Not connected
47
SC4_IN_L
I
SCART 4 input, left
48
SC4_IN_R
I
SCART 4 input, right
49
ASG
—
Analog Shield Ground
50
SC3_IN_L
I
SCART 3 input, left
51
SC3_IN_R
I
SCART 3 input, right
52
ASG
—
Analog Shield Ground
53
SC2_IN_L
I
SCART 2 input, left
54
SC2_IN_R
I
SCART 2 input, right
55
ASG
—
Analog Shield Ground
56
SC1_IN_L
I
SCART 1 input, left
57
SC1_IN_R
I
SCART 1 input, right
58
NC
—
Not connected
59
VREFTOP
—
Reference voltage IF A/D converter
60
MONO_IN
I
Mono input
61,62
AVSS
—
Analog ground
63,64
NC
—
Not connected
65,66
AVSUP
—
Analog power supply 5V
67
ANA_IN1+
I
IF input 1
68
ANA_IN-
I
IF common(can be left vacant, only if IF input 1 is also not in use)
69
ANA_IN2+
I
IF input 2(can be left vacant, only if IF input 1 is also not in use)
70
TESTEN
I
Test pin
71
XTAL_IN
I
C
rystal oscillator
72
XTAL_OUT
O
73
TP
—
Test pin
74
AUD_CL_OUT
O
Audio clock output(18.432MHz)
75,76
NC
—
Not connected
77
D_CTR_I/O_1
I/O
D_CTR_I/O_1
78
D_CTR_I/O_0
I/O
D_CTR_I/O_0
79
ADR_SEL
I
I2C Bus address select
80
STANDBYQ
I
Stand-by(low-active)
65
65-1
65-2
LC-37AD1E
Ë
RH-IX3289CEZZ(ASSY:IC7200)
Auto Wide IC
»
Block Diagram
Pin No
.
P
in Name
I/O
Pin Function
»
Pin Function
1
GND
—
Ground
2
VCC
—
Power supply(3.3V)
3
CKIN
I
4
CKOUT
O
5
VCC
—
Power supply(3.3V)
6
GND
—
Ground
7
TEST
I
N
.C
8
ASD0
O
A
WDATA
9
TPI
I
AWCS_W
10
TCI
I
D_CLK
11
TDI
I
D_DATAOUT
12
SIREI
I
AWCS_R
13
VCC
—
Power supply(3.3V)
14
HER1
O
N
.C
15
HER2
O
N
.C
16
VMSET
I
N
.C
17
VCKIN
I
Ground
18
VCKO
O
N
.C
19
VDIN
I
VDIN
20
HD
I
H
D
21
HOVBLK
O
N
.C
22
GND
—
Ground
23
TESTOUT
O
N
.C
24
GND
—
Ground
25
OUT0
O
N
.C
26
OUT1
O
N
.C
27
VCC
—
Power supply(3.3V)
28
OUT2
O
N
.C
29
OUT3
O
N
.C
30
OUT4
O
N
.C
31
VTS
I
N
.C
32
HTS
I
N
.C
33
OUTSWI
I
N
.C
34
ASDOCNTOUT
O
ASDOCNTOUT
35
DIA
I
N.C
36
MTESTI
I
N
.C
37
ANSWIO
I
ANSWIO
38
ANSWOI
O
ANSWOI
39
GND
—
Ground
40
PRS
I
PRS
41
IPIN
I
N
.C
42
VCC
—
Power supply(3.3V)
43
HIN
I
AT_HD
44
VIN
I
AT_VD
Ë
RH-IX3270CEZZ (ASSY:IC10001)
32bit RISC Micro Processor
»
Block Diagram
66
66-1
66-2
LC-37AD1E
Pin No
.
Pin Name
I/O
Pin Function
»
Pin Function
34,36-44,
D[15:0]
I/O
Data bus D[15:0]
46,48-52
23-26,28,30-32
D[23:16/PTA[7:0]
I/O
Data bus D[23:16]/I/O port A[7:0]
13-18,20,22
D[31:24/PTB[7:0]
I/O
Data bus D[31:24]/I/O port B[7:0]
86,84,82,78-72,
A[25:0]
O
Address bus A[15:0]
70-68-60,56-53
96
CS0
O
Chip select 0
98
CS2/PTK[0]
O/(I/O)
Chip select 2/I/O port K[0]
99
CS3/PTK[1]
O/(I/O)
Chip select 3/I/O port K[1]
100
CS4/PTK[2]
O/(I/O)
Chip select 4/I/O port K[2]
101
CS5/CE1E/PTK[3]
O/(I/O)
Chip select 5/CE1(area 5SPCMIA)/O port K[3]
102
CS6/CE1B
0
Chip select 6/CE1(area 6SPCMIA)
87
BS/PTK[4]
O/(I/O)
Bus cycle startup signal /I/O port K[4]
118
RAS3U/PTE[2]
O/(I/O)
"RAS(area 3DRAM,SDRAM upper 32MB address)/I/O port E[2}"
106
RAS3L/PTJ[0]
O/(I/O)
"RAS(area 3DRAM,SDRAM upper 32MB address)/I/O port J[0}"
119
RAS2U/PTE[1]
O/(I/O)
"RAS(area 2DRAM,SDRAM upper 32MB address)/I/O port E[1}"
107
RAS2L/PTJ[1]
O/(I/O)
"RAS(area 2DRAM,SDRAM upper 32MB address)/I/O portJE[1}"
108
CASLL/CAS/PTJ[2]
O/(I/O)
CAS(DRAM)/CAS(SDRAM)/I/O port J[2] for D7-D0.
110
CASLH/PTJ[3]
O/(I/O)
CAS(DRAM)/I/O port J[3] for D15-D18.
112
CASHL/PTJ[4]
O/(I/O)
CAS(DRAM)/I/O port J[4] for D23-D16.
113
CASHH/PTJ[5]
O/(I/O)
CAS(DRAM)/I/O port J[5] for D31-D24.
116
CAS2L/PTE[6]
O/(I/O)
CAS(area 2DRAM)/I/O port E[6] for D7-D0.
117
CAS2H/PTE[3]
O/(I/O)
CAS(area 2DRAM)/I/O port E[3] for D15-D8.
89
WE0/DQMLL
O
D7-D0 selection signal/DQM(SDRAM)
90
WE1/DQMLU/WE
O
D15-D8 selection signal/DQM(SDRAM)/PCMCIA WE
91
WE2/DQMUL/
O/(I/O)
D23-D16 selection signal/DQM(SDRAM)/PCMCIA I/O port K[6]
ICIORD/PTK[6]
92
WE3/DQMUU/
O/(I/O)
D31-D24 selection signal/DQM(SDRAM)/PCMCIA I/O write/I/O port K[7]
ICIOWR/PTK[7]
93
RD/WR
O
Read/write change signal
88
RD
O
Read strobe
105
CKE/PTK[5]
O/(I/O)
CK enable(Only for SDRAM)/I/O port K[5]
123
WAIT
I
Hardware weight demand.
11-8
IRL[3:0]/IRQ[3:0]/
I
E
xternal interruption demand/I/OportH[3:0]
PTH[3:0]
12
IRQ4/PTH[4]
I
External interruption demand/I/OportH[4]
7
NMI
I
Non maskable interruption demand.
160
IRQOUT
O
Interruption demand output
182
WAKEUP/PTD[3]
O/(I/O)
Interruption demand output at the time of standby mode/I/OportD[3]
159
TCLK/PTH[7]
I/O
Clock input output/I/OportH[7] for TMU/RTC.
191
DREQ0/PTD[4]
I
DMA demand 0/I/OportD[4]
114
DACK0/PTD[5]
O/(I/O)
DMA acknowledge 0/I/O port D[5]
192
DREQ1/PTD[6]
I
DMA demand 0/I/O port D[6]
115
DACK1/PTD[7]
O/(I/O)
DMA acknowledge 1/I/O port D[7]
189
DRAK0/PTD[1]
O/(I/O)
DMA acknowledge 0/I/O port D[1]
190
DRAK1/PTD[0]
O/(I/O)
DMA acknowledge 0/I/O port D[0]
171
RxD0/SCPT[0]
I
Input port [0] for receiving data 0/SCI.
164
TxD0/SCPT[0]
O
Output port [0] for transmission data 0/SCI.
165
SCK0/SCPT[1]
I/O
I/O port [1] for serial clock 0/SCI.
172
RxD1/SCPT[2]
I
Input port [2] for receiving data 1/SCI.
166
TxD1/SCPT[2]
O
Output port [2] for transmission data 1/SCI.
167
SCK1/SCPT[1]
I/O
I/O port [3] for serial clock 1/SCI.
174
RxD2/SCPT[4]
I
Input port [4] for receiving data 2/SCI.
168
TxD2/SCPT[4]
O
Output port [4] for transmission data 2/SCI.
169
SCK2/SCPT[5]
I/O
I/O port [5] for serial clock 2/SCI.
170
RTS2/SCPT[6]
O/(I/O)
Requests to Send 2/for SCI/I/O port [6]
176
CTS2/IRQ5/SCPT[7]
I
Transmitting clearance 2/an external interruption demand/Input port [7] for SCI.
104
CE2B/PTE[5]
O/(I/O)
Chip enable 2/I/O port E[5] for Pc card 0.
126
IOIS16/PTG[7]
I
Write protection/Input port G[7]
103
CE2A/PTE[[4]
O/(I/O)
Chip enable 2/I/O port E[4] for PC card 1.
146,149
CAP[1:2]
—
External capacity terminal for PLL [1:2]
156
EXTAL
I
External clock/Crystal oscillation element terminal
155
XTAL
O
Crystal oscillation element terminal
162
CKIO
I/O
System clock input and output
5
EXTAL2
I
C
rystal oscillation element terminal for RTC.
4
XTAL
O
Crystal oscillation element terminal for RTC.
193
RESETP
I
Power-on reset demand
124
RESETM
I
Manual reset demand
Pin No
.
Pin Name
I/O
Pin Function
19
EXT_SWING
Voltage Swing Adjust. A resistor should tie this pin to AVCC. This resistor
determines the amplitude of the voltage swing. A 510 ohm resistor is
recommended for remote display applications. For notebook computers, 680
ohm is recommended.
11
MSEN
O
Monitor Sense. This pin is an open collector output. The output is
programmable through the I2C interface (see I2C register definitions).
An external 5k pull-up resistor is required on this pin.
34
RESERVED
I
This pin is reserved for Silicon Image use only and should be tied LOW for
normal operation.
7,8
NC
—
These pins are not electrically connected inside the package.
13
ISEL/RST#
I
I2C Interface Select. If HIGH, then the I2C interface is active.
15
SCLS
I
DDC I2C Clock. This pin is a slave I2C clock line which interfaces to the DDC
bus for communicating with a host side master. HDCP KSV, An, and Ri values
are exchanged over this DDC bus during authentication. The clock may be run
up to 400kHz. This pin is not 5V-tolerant; it should be connected through a level
shifter to the DDC clock line SCL. This is an open-collector pin.
14
SDAS
I/O
DDC I2C Data. This pin is a slave I2C data line for communicating with a host
side master. HDCP KSV, An and Ri values are exchanged over this DDC bus
during authentication. Data may be clocked in at up to 400kHz. This pin is not
5V-tolerant; it should be connected through a level shifter to the DDC clock line
SDA. This is an open-collector bi-directional pin, and is not made high-
impedance when PD#=LOW.
6
CTL3
I
External CTL3. This pin is used to bring in the CTL3 signal for HDCP when the
HDCP encryption is performed before the video enters the SiI 170. To enable
this input, the CTL3 bit must be programmed in Reg[0x08]. If the CTL3 bit is
cleared, then this input pin is ignored and may be left unconnected. This pin is
a regular high swing (3.3V) input, containing a weak pull-down resistor so that if
left unconnected it will default to LOW.
9
HTPLG
I
Monitor Charge Input. This pin is used to connect to the DVI Hot Plug pin to
detect the presence of an attached monitor.
1,12,33
VCC
—
Digital VCC. Connect to 3.3V supply.
16,35,64
GND
—
Digital GND.
23,29
AVCC
—
Analog VCC. Connect to 3.3V supply.
20,26,32
AGND
—
Analog GND.
18
PVCC1
—
Primary PLL Analog VCC. Connect to regulated 3.3V supply.
49
PVCC2
—
Filter PLL Analog VCC. Connect to regulated 3.3V supply.
17
PGND1
—
PLL Analog GND.
48
PGND2
—
PLL Analog GND.
67
67-1
67-2
LC-37AD1E
Ë
9DK001-15079(CXA3506R) (ASSY:IC10004)
3ch 8bit 120MSPS A/D CONVERTER AMP. PLL
»
Block Diagram
»
Pin Function
Pin No
.
Pin Name
I/O
Pin Function
1
B
/CbOUT
O
Amplifier output signal monitor
2
ADDRESS
I
I2C slave address setup
3
R/CrOUT
O
Amplifier output signal monitor
4N
C
—
Not connected
5N
C
—
Not connected
6
XPOWERSAVE
I
P
ower save setup
7
D
GNDREG
—
GND for registers
8
DVCCREG
—
Power supply for registers
9
SDA
I
Control register data input
10
SCL
I
Control register clock signal input
11
XSENABLE
I
Enable signal input for 3 line control registers
12
SEROUT
O
3
line control register data read-out
13
3WIRE/I2C
I
Selection in I2C-bus mode and 3 line bus mode
15
AVCCADREF
—
Power supply for reference voltage of ADC
16,94
AVCCAD3
—
Analog power supply of ADC
17
VRT
O
The top reference voltage output of ADC
18,92
DVCCAD3
—
Digital power supply of ADC
19,32,42,54,
DVCCADTTL
—
Power supply for a TTL output of ADC
65,76,90
20,33,44,55,
DGNDADTTL
—
GND for a TTL output of ADC
67,77,89
21,22,24-28,31
RA0~RA7
O
R
channel port A side data output
23,30,43,50,
DGNDAD3
—
Digital GND of ADC
59,66,79,86
29,80
AGNDAD3
—
Analog GND of ADC
34-41
RB0~RB7
O
R
channel port B side data output
Pin No
.
Pin Name
I/O
Pin Function
45-49,51-53
BA0~BA7
O
B
channel port A side data output
56-58,60-64
BB0~BB7
O
B
channel port B side data output
68-75
GA0~GA7
O
G
channel port A side data output
78,81-85,87,88
GB0~GB7
O
G
channel port B side data output
91
DVCCAD
—
Digital power supply of ADC
93
VRB
O
Bottom reference voltage output of ADC
95
AGNDADREF
—
GND for reference voltage of ADC
96
DVCCPLLTTL
—
Power supply for a TTL output of PLL
97
DGNDPLLTTL
—
Power supply for a TTL output of PLL
98
XCLKCLK
O
CLK reversal output
99
1/2XCLK
O
CLK output
100
1/2CLK
O
1/2 CLK reversal output
101
DSYNC/
O
1/2 CLK output
103
DIVOUT
O
DSYNC signal output /DIVOUT signal output.
104
UNLOCK
O
UNLOCK signal output terminal.
105
SOGOUT
O
Sync signal output of a sync-on green signal.
106
HOLD
I
Input of the de-sable signal of phase comparison.
107
XTLOAD
I
Reset setup of a programmable counter.
108
EVEN/ODD
I
Sampling clock reversal pulse input of ADC.
109
XCLKIN
I
Negative clock input for a test.
110
CLKIN
I
Positive clock input for a test.
111
SYNCIN1
I
S
ync signal input1
112
SYNCIN2
I
Sync signal input2
113
CLPIN
I
Clamp pulse input.
114
DVCCPLL
—
Digital power supply for PLL.
115
DGNDPLL
—
Digital GND for PLL.
116
AVCCVCO
—
Analog power supply for VCO of PLL.
117
AGNDVCO
—
Analog GND for VCO of PLL.
118
RC1
—
PLL loop filter external terminal-1.
119
RC2
—
PLL loop filter external terminal-2.
120
AVCCIR
—
Analog power supply for IREF
121
IREF
I
Current setup
123
AGNDIR
—
Analog GND for IREF
124
G/YIN1
I
G/Y signal input-1
125
AVCCAMPG
—
Power supply for G/Y amplifier parts
126
G/YIN2
I
G/Y signal input-2
127
AGNDAMPG
—
GND for G/Y amplifier parts
128
G/YCLP
—
Clamp capacitor connection terminal for brightness
129
B/CbCLP
—
Clamp capacitor connection terminal for brightness
130
R/CrCLP
—
Clamp capacitor connection terminal for brightness
132
SOGIN1
I
sync-on green signal input-1.
133
B/CbIN1
I
B/Cb signal input-1
134
AVCCAMPB
—
Power supply for B/Cb amplifier parts
135
SOGIN2
I
sync-on green signal input-2.
136
B/CbIN2
I
B/Cb signal input-2
137
AGNDAMPB
—
GND for B/Cb amplifier parts
139
R/CrIN1
I
R/Cr signal input-1
140
AVCCAMPR
—
Power supply for R/Cr amplifier parts
141
R/CrIN2
I
R
/Cr signal input-2
142
AGNDAMPR
—
GND for R/Cr amplifier parts
143
G/YOUT
O
A
mplifier output signal monitor
144
DACTEST
O
Test output terminal of DAC for amplifier part control registers
14,102,122,
OUTDPGND
—
GND
131,138
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