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LC-26D44E/S/RU-BK/GY

5 – 5

• HDCP Built in Self Test (BIST) lowers cost to test HDCP operation.

• Pre-programmed HDCP keys provide highest level of key security, simplifies manufacturing.

Digital Video Output Pins.

144, 143, 142, 141, 140, 137, 136, 133, 132, 131, 

130, 129, 126, 125, 124, 123, 119, 118, 117, 116, 

113, 112, 111, 110

Q0-23

O

24-bit Output Pixel Data Bus.

1

DE

O

Data enable.

2

HSYNC

O

Horizontal Sync Output control signal.

3

VSYNC

O

Vertical Sync Output control signal.

121

ODCK

O

Output Data Clock.

Digital Audio Output Pins.

97

XTALIN

I

Crystal Clock Input.

96

XTALOUT

O

Crystal Clock Output.

88

MCLKOUT

O

Audio Master Clock Output.

86

SCK

O

I2S Serial Clock Output.

85

WS

O

I2S Word Select Output.

84

SD0

O

I2S Serial Data Output.

78

SPDIF

O

S/PDIF Audio Output.

77

MUTEOUT

O

Mute Audio Output.

Configuration/Programming Pins.

104

INT

O

Interrupt Output.

102

RESET#

I

Reset Pin. Active LOW.  5V Tolerant.

32

DSCL0

I

DDCI2C Clock for Port 0.  5V Tolerant.

31

DSDA0

I/O

DDCI2C Data for Port 0.  5V Tolerant.

30

DSCL0

I

DDCI2C Clock for Port 1.  5V Tolerant.

29

DSDA1

I/O

DDCI2C Data for Port 1.  5V Tolerant.

28

CSCL

I

Configuration I2C Clock.  5V Tolerant.

27

CSDA

I/O

Configuration I2C Data.  5V Tolerant.

103

SCDT

O

Indicates active video at HDMI input  port.

107

CLK48B

I/O

Data Bus Latch Enable.

34

R0PWR5V

I

Port 0 Transmitter Detect. 5V Tolerant.

33

R1PWR5V

I

Port 1 Transmitter Detect. 5V Tolerant.

101

RSVDL

I

Reserved, must be tied LOW.

56

RSVD_A

Reserved Pin, leave unconnected.

6, 7, 8, 10, 11, 12, 13, 14, 17, 18, 19, 20, 81, 82, 

83, 87, 93, 100

NC

---

No internal connection.

9

EVNODD

O

Indicates. Even or Odd field for interlaced formats. Polarity pro-
grammable in register.

Differential Signal Data Pins.

40

R0XC+

I

HDMI Port 0. TMDS input clock pair.

39

R0XC-

I

44

R0X0+

I

HDMI Port 0. TMDS input data pair.

43

R0X0-

I

48

R0X1+

I

HDMI Port 0. TMDS input data pair.

47

R0X1-

I

52

R0X2+

I

HDMI Port 0. TMDS input data pair.

51

R0X2-

I

59

R1XC+

I

HDMI Port 1. TMDS input clock pair.

58

R1XC-

I

63

R1X0+

I

HDMI Port 1. TMDS input data pair.

62

R1X0-

I

67

R1X1+

I

HDMI Port 1. TMDS input data pair.

66

R1X1-

I

71

R1X2+

I

HDMI Port 1. TMDS input data pair.

70

R1X2-

I

Power and Ground Pins.

22, 23, 35, 74, 79, 92, 105, 114, 128, 139

CVCC18

---

Digital Logic VCC.

21, 24, 36, 73, 80, 91, 106, 115, 127, 138

CGND

---

Digital Logic GND.

5, 16, 26, 76, 89, 109, 122, 134

IOVCC

---

Input/Output Pin Supply(3.3V).

4, 15, 25, 75, 90, 108, 120, 135

IOGND

---

Input/Output Pin Ground.

38, 42, 46, 50, 57, 61, 65, 69

AVCC

---

TMDS Analog VCC.

41, 45, 49, 53, 60, 64, 68, 72

AGND

---

TMDS Analog GND.

37

PVCC0

---

TMDS Port 0 PLL VCC.

55

PVCC1

---

TMDS Port 1 PLL VCC.

LC-26D44E/S/RU-BK/GY

5 – 6

The RH-IXC009WJZZQ is a high-speed and high-performance 8-bit single-chip microcomputer with a built-in 61440-byte flash memory.

In this equipment, the R/C LED on the AVC side and system on the display side are controlled.

54

TMDSPGND

---

TMDS PLL GND.

94

AUDPVCC18

---

ACR PLL VCC.

95

AUDPGND

---

ACR PLL GND.

98

XTALVCC

---

ACR PLL Crystal Input VCC.

99

REGVCC

---

ACR PLL Regulator VCC.

1

GND

---

Ground.

2

8MHz_IN

I

Crystal oscillator input.

3

8MHz_OUT

O

Crystal oscillator output.

4

TEST

I

Terminal for shipping test. Fixed to “L” level.

5

3.3V

---

Power supply (+3.3V).

6

FRC_BUS_SW

O

N.C.

7

32kHz_OUT

O

N.C.

8

RESET

I

RESET input terminal.

9

P20

---

N.C.

10

P00

---

N.C.

11

UART-RXD1

I

For flash write.

12

UART-TXD1

O

For flash write.

13

CEC-IN

I

CEC.

14

P04

I

N.C.

15

P05

O

N.C.

16

CEC-OUT

O

N.C.

17

CEC-IN2

I

N.C.

18

VAREF

---

Power supply (+3.3V).

19

AVDD

---

Power supply (+3.3V).

20

AIN0

I

Temperature sensor.

21

AIN1

I

N.C.

LC-26D44E/S/RU-BK/GY

5 – 7

22

AIN2

I

N.C.

23

AIN3

I

N.C.

24

AC_DET

I

Power supply detection.

25

ANT_ERR

I

ANT5V short detection.

26

BL_ERR

I

Backlight detection.

27

SV1JSW

I

S-terminal detection.

28

QS_EN

O

Panel controller QS.

29

FRAME

O

50/60Hz select.

30

T1

I

Panel controller TEMP.

31

T2

I

Panel controller TEMP.

32

T3

I

Panel controller TEMP.

33

BANK_SEL

O

Panel controller

34

R/L

O

Panel controller. Flip horizontal.

35

U/D

O

Panel controller. Flip vertical.

36

EXT_DTV

O

DTV_etc. select (H,V,Audio)

37

HDMI_PC

O

HDMI-PC select (H,V,Audio)

38

SCART12

O

SCARTselect.

39

PE

O

Panel enable.

40

HP_MUTE

O

Mute. Headphono.

41

ANT+5V_SW

O

ANT+5V control

42

DTN_BUS_SEL

O

D-TUNER I2C select

43

DTM_RST

O

DTV PWB reset

44

TCON_WP

O

Counter adjustment write-protect

45

LVDS_EN

O

N.C

46

CONT_DET

---

N.C

47

PS_ON

O

Power_on.

48

PCON1

O

DC-DC_on.

49

TEST

O

N.C

50

LCD_POW

O

N.C

51

12V_DET

O

LCD_12V detection.

52

SCL

I

I2C Slave clock

53

SDA

I/O

I2C Slave data

54

I-REQ

O

Sub-microprocessor interrupt

55

SCL_F

I

N.C. (Pull-up)

56

SDA_F

I/O

N.C. (Pull-up)

57

LEDPOW_R

O

Power R_LED ON.

58

LEDPOW_G

O

Power G_LED ON.

59

LEDSLP

O

N.C.

60

LEDOPC

O

N.C.

61

MUTE_SP

O

Mute.

62

S_MUTE

O

Mute.

63

S2_MUTE

O

Mute SCART2.

64

IREM_SW

O

N.C.

LC-26D44E/S/RU-BK/GY

5 – 8

High-efficiency digital audio power amplifier IC with maximum power output of 20W (Vddp=14V, RL=4

Ω) x 2ch.

It incorporates the “DRC (Dynamic range compression)” function. Since the volume is increased at low volume level and is decreased at high volume
level, it is possible to prevent sudden volume change. It is also provided with the “power limiter” which can set the output limit.

1, 2, 12, 25, 35, 36

NC

---

No connection.

3

PVDDREG

---

Power terminal for regulator (PVDD).

4

AVDD

---

Output terminal for 3.3V regulator.

5

INLP

I

Analog input terminal (Lch+)

6

INLM

I

Analog input terminal (Lch-)

7

VREF

VREF terminal.

8

INRM

I

Analog input terminal (Rch-)

9

INRP

I

Analog input terminal (Rch+)

10

AVSS

---

GND terminal for analog.

11

PLIMIT

I

Power limit setting terminal.

13, 14

PVDDPR

---

Power terminal for digital amplifier output (Rch+).

15, 16, 17

OUTPR

O

Digital amplifier output terminal (Rch+).

18, 19

PVSSR

---

Ground terminal for digital amplifier output (Rch).

20, 21, 22

OUTMR

O

Digital amplifier output terminal (Rch-).

23, 24

PVDDMR

---

Power terminal for digital amplifier output (Rch-).

26

SLEEPN

I

Sleep control terminal.

27

PROTN

O

Error flag output terminal.

28

MUTEN

I

Mute control terminal.

29

CKOUT

O

Clock output terminal for synchronization.

30

CKIN

I

External clock input terminal.

31

NCDRC0

I

Non-clip/DRC1/DRC2 mode selection terminal 0.

32

NCDRC1

I

Non-clip/DRC1/DRC2 mode selection terminal 1.

33

GAIN0

I

GAIN setting terminal 0.

34

GAIN1

I

GAIN setting terminal 1.

37, 38

PVDDML

---

Power terminal for digital amplifier output (Lch-).

39, 40, 41

OUTML

O

Digital amplifier output terminal (Lch-).

42, 43

PVSSL

---

Ground terminal for digital amplifier output (Lch).

44, 45, 46

OUTPL

O

Digital amplifier output terminal (Lch+).

47, 48

PVDDPL

---

Power terminal for digital amplifier output (Lch+).