Sharp LC-26D44E (serv.man6) Service Manual ▷ View online
LC-26D44E/S/RU-BK/GY
5 – 13
10. IC4001 (RH-IXC243WJZZQ)
This is a video/ audio signal processing IC (Set-top-box decoder) for digital tuner, incorporates a CPU. In this equipment, it implements GUI process-
ing and video/audio processing for digital tuner, negotiation processing with CI-CARD, etc.
ing and video/audio processing for digital tuner, negotiation processing with CI-CARD, etc.
Pin No.
Pin Name
I/O
Pin Function
System pins
138
CLK27IN
I
27 MHz crystal circuit.
139
CLK27OUT
O
27 MHz crystal circuit.
128
AUXCLKOUT
O
Auxiliary clock for general use.
130
NOT_RESET
I
System reset.
131
NOT_RSTOUT
O
Reset out.
FMI pins
89
FMIDATA15
I/O
Bidirectional data.
90
FMIDATA14
I/O
91
FMIDATA13
I/O
92
FMIDATA12
I/O
93
FMIDATA11
I/O
94
FMIDATA10
I/O
95
FMIDATA9
I/O
97
FMIDATA8
I/O
98
FMIDATA7
I/O
99
FMIDATA6
I/O
100
FMIDATA5
I/O
103
FMIDATA4
I/O
104
FMIDATA3
I/O
105
FMIDATA2
I/O
106
FMIDATA1
I/O
107
FMIDATA0
I/O
56
FMIADDR23
O
Address (8 Mbyte).
57
FMIADDR22
O
58
FMIADDR21
O
59
FMIADDR20
O
60
FMIADDR19
O
61
FMIADDR18
O
62
FMIADDR17
O
63
FMIADDR16
O
64
FMIADDR15
O
65
FMIADDR14
O
66
FMIADDR13
O
69
FMIADDR12
O
70
FMIADDR11
O
71
FMIADDR10
O
73
FMIADDR9
O
74
FMIADDR8
O
75
FMIADDR7
O
76
FMIADDR6
O
77
FMIADDR5
O
78
FMIADDR4
O
79
FMIADDR3
O
80
FMIADDR2
O
81
FMIADDR1
O
52
NOT_FMICSD
O
Chip select.
51
NOT_FMICSC
O
50
NOT_FMICSB
O
49
NOT_FMICSA
O
88
NOT_FMIOE
O
Output enable.
86
NOT_FMIBE1
O
Byte enable.
87
NOT_FMIBE0
O
85
NOT_FMILBA
O
Flash device load burst address.
83
FMIRDNOTWR
O
Read not write.
82
FMIWAIT
I
Wait input (extend read/write cycle).
53
FMIFLASHCLK
O
Peripheral clock.
LMI pins
LC-26D44E/S/RU-BK/GY
5 – 14
201
LMIDATA15
I/O
Bidirectional data.
199
LMIDATA14
I/O
198
LMIDATA13
I/O
197
LMIDATA12
I/O
194
LMIDATA11
I/O
192
LMIDATA10
I/O
191
LMIDATA9
I/O
190
LMIDATA8
I/O
180
LMIDATA7
I/O
178
LMIDATA6
I/O
175
LMIDATA5
I/O
174
LMIDATA4
I/O
171
LMIDATA3
I/O
Bidirectional data.
169
LMIDATA2
I/O
168
LMIDATA1
I/O
167
LMIDATA0
I/O
208
LMIADDR12
O
Address.
209
LMIADDR11
O
157
LMIADDR10
O
210
LMIADDR9
O
211
LMIADDR8
O
213
LMIADDR7
O
214
LMIADDR6
O
215
LMIADDR5
O
216
LMIADDR4
O
150
LMIADDR3
O
152
LMIADDR2
O
153
LMIADDR1
O
154
LMIADDR0
O
159
LMIBA1
O
Bank select.
160
LMIBA0
O
182
LMIDQM0
O
Data I/O mask lower.
186
LMIDQM1
O
Data I/O mask upper.
181
LMIDQS0
O
Data strobe lower.
188
LMIDQS1
O
Data strobe upper.
162
NOT_LMICS
O
Chip select.
163
NOT_LMIRAS
O
Latch row address strobe.
164
NOT_LMICAS
O
Latch column address strobe.
206
LMICLKEN
O
Clock enable.
203
LMICLK
O
Clock.
202
NOT_LMICLK
O
Inverted clock.
183
LMI_VREF
I
Input reference voltage.
166
LMIRDNOTWR
O
Write enable signal.
Analog audio DAC pins
28
OUTLMINUS
O
Audio DAC left differential current output.
24
OUTRMINUS
O
Audio DAC right differential current output.
29
OUTLPLUS
O
Audio DAC left differential current output.
25
OUTRPLUS
O
Audio DAC right differential current output.
23
VGBOUT
O
Audio DAC filtered output reference voltage.
26
IREFADAC
I
Current reference for Audio DAC.
Digital audio pins
37
S/PDIF
O
Digital audio.
Analog video DAC pins
15
VDAC1OUT
O
Video DAC outputs.
16
VDAC2OUT
O
17
VDAC3OUT
O
18
VDAC4OUT
O
14
GNDREXTVDAC
I
Video DAC external resistor ground.
13
REXTVDACRGB
I
VDAC external resistor input.
Transport stream pins
35
TS0INBITCLK
I
TSIN0 Parallel//Serial in.
33
TS0INBITCLKVALI
D
D
I
34
TS0INPACKETCLK
I
36
TS0INDATA7
I
Pin No.
Pin Name
I/O
Pin Function
LC-26D44E/S/RU-BK/GY
5 – 15
Programmable I/O pins
127
POI0[7]
I/O
PIO PORT 0
126
PIO0[6]
123
PIO0[5]
122
PIO0[4]
121
PIO0[3]
120
PIO0[2]
119
PIO0[1]
118
PIO0[0]
46
PIO1[7]
I/O
PIO PORT 1
45
PIO1[6]
44
PIO1[5]
43
PIO1[4]
41
PIO1[3]
40
PIO1[2]
39
PIO1[1]
38
PIO1[0]
117
PIO2[7]
I/O
PIO PORT 2
116
PIO2[6]
115
PIO2[5]
114
PIO2[4]
111
PIO2[3]
110
PIO2[2]
109
PIO2[1]
108
PIO2[0]
12
PIO3[6]
I/O
PIO PORT 3
11
PIO3[5]
10
PIO3[4]
7
PIO3[3]
6
PIO3[2]
5
PIO3[1]
4
PIO3[0]
JTAG test access port (TAP) pins
134
TDI
I
TAP boundary scan test data input.
133
TMS
I
TAP boundary scan test mode select.
137
TCK
I
TAP boundary scan test clock.
135
NOT_TRST
I
TAP boundary scan test logic reset.
132
TDO
O
TAP boundary scan test data output.
DCU pins
1
DCUTRIGGERIN
I
External trigger input to DCU.
2
DCUTRIGGEROUT
O
Signal to trigger external debug circuitry.
Analog power supply pins (Audio DAC)
32
VDDAADAC
---
3.3v power for audio DAC.
31
GNDAADAC
---
Ground for audio DAC.
30
VSSUBANA
---
Substrate ground for all DACs.
Analog power supply pins (Video DAC)
22
VDDDAC0
---
3.3 V power supply for video DAC 1, 2 and 3.
21
VDDDAC1
---
3.3 V power supply for CVBS video DAC 4.
19
VSSDAC0
---
Ground for video DAC 1, 2 and 3.
20
VSSDAC1
---
Ground for video DAC 4.
Analog power supply pins (Frequency synthesizers)
140
VDDDFS1
---
Frequency synthesizer 1.2 V digital power dedicated to frequency synthesizer 1.
141
GNDDFS1
---
Frequency synthesizer 1.2 V digital ground dedicated to frequency synthesizer 1.
142
VCCAFS
---
Frequency synthesizer 1.2 V analog power shared between frequency synthesizer
1 and 2.
1 and 2.
143
GNDAFS
---
Frequency synthesizer 1.2 V analog ground shared between frequency synthe-
sizer 1 and 2.
sizer 1 and 2.
144
GNDDFS2
---
Frequency synthesizer 1.2 V digital ground dedicated to frequency synthesizer 2.
145
VDDDFS2
---
Frequency synthesizer 1.2 V digital power dedicated to frequency synthesizer 2.
Analog power supply pins (PLLs)
146
VCCAPLL
---
1.2V PLL1 analog power.
147
GNDAPLL
---
1.2V PLL1 analog ground.
148
GNDAPLL1
---
1.2V PLL2 analog ground.
149
VCCAPLL1
---
1.2V PLL2 analog power.
Analog power supply pins (LMI SDRAM)
Pin No.
Pin Name
I/O
Pin Function
LC-26D44E/S/RU-BK/GY
5 – 16
11. IC4201 (RH-IXB765WJQZQ)
This IC is 256Mb H-die DDR SDRAM (static dynamic random-access memory) IC.
In this equipment, it is used for LMI memory (for image processing), and data is used for operation of the Set-top-box decoder.
184
VDDDLL
---
1.2 V for DLL.
185
GNDDLL
---
Ground for DLL.
176
VDDDE0
---
1.2 V for delay element 1.
177
VSSDE0
---
Ground for delay element 1.
196
VDDDE1
---
1.2 V for delay element 2.
195
VSSDE1
---
Ground for delay element 2.
Digital power supply pins
8, 47, 67, 101, 124, 155, 173,
204
VDD12
---
1.2 V digital power supply.
151, 158, 165, 170, 179, 187,
193, 200, 207, 212
VDD25
---
2.5 V power supply when connected to DDR SDRAM on the LMI interface.
3, 42, 55, 72, 84, 96, 113, 129
VDD33
---
3.3 V power supply.
EP1, 9, 27, 48, 54, 68, 102,
112, 125, 136, 156, 161, 172,
189, 205
GND
---
Ground.
Pin No.
Pin Name
I/O
Pin Function
45, 46
CK, CK
I
Clock : CK and CK are differential clock inputs.
44
CKE
I
Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock
signals, and device input buffers and output drivers.
signals, and device input buffers and output drivers.
24
CS
I
Chip Select : CS enables (registered LOW) and disables (registered HIGH) the
command decoder.
command decoder.
23-21
RAS, CAS, WE
I
Command Inputs : RAS, CAS and WE (along with CS) define the command
beingentered.
beingentered.
20, 47
LDM, (UDM)
I
Input Data Mask.
26, 27
BA0, BA1
I
Bank Addres Inputs.
29, 30, 31, 32, 35, 36, 37, 38, 39, 40,
28, 41, 42
A [0:12]
I
Address Inputs.
2, 4, 5, 7, 8, 10, 11, 13, 54, 56, 57,
59, 60, 62, 63, 65
DQ[0:15]
I/O
Data Input/Output : Data bus.
16, 51
LDQS, (U)DQS
I/O
Data Strobe : Output with read data, input with write data.
14, 17, 19, 25, 43, 50, 53
NC
---
No Connect : No internal electrical connection is present.
3, 9, 15, 55, 61
VDDQ
---
DQ Power Supply.
6, 12, 52, 58, 64
VSSQ
---
DQ Ground.
1, 18, 33
VDD
---
Power Supply.
34, 48, 66
VSS
---
Ground.
49
VREF
I
SSTL_2 reference voltage.
Pin No.
Pin Name
I/O
Pin Function
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