Sharp LC-26D44E (serv.man6) Service Manual ▷ View online
LC-26D44E/S/RU-BK/GY
5 – 17
LC-26D44E/S/RU-BK/GY
5 – 18
12. IC4251 (RH-IXC361WJZZQ)
This IC is a high performance CMOS super technology 16Mbit Flash Memory.
Start software (loader) for the CPU with a built-in digital processor and application software have been written on this Flash Memory.
The digital processor reads these soft wares on start-up and implements them.
13. IC4410 (VHIAOZ1320C-1Y)
Load Switch with Controlled Slew Rate IC
Pin No.
Pin Name
I/O
Pin Function
25
A0
I
Address Inputs.
24
A1
I
23
A2
I
22
A3
I
21
A4
I
20
A5
I
19
A6
I
18
A7
I
8
A8
I
7
A9
I
6
A10
I
5
A11
I
4
A12
I
3
A13
I
2
A14
I
1
A15
I
48
A16
I
17
A17
I
16
A18
I
9
A19
I
29
DQ0
I/O
Data inputs/Outputs.
31
DQ1
I/O
33
DQ2
I/O
35
DQ3
I/O
38
DQ4
I/O
40
DQ5
I/O
42
DQ6
I/O
44
DQ7
I/O
30
DQ8
I/O
32
DQ9
I/O
34
DQ10
I/O
36
DQ11
I/O
39
DQ12
I/O
41
DQ13
I/O
43
DQ14
I/O
45
DQ15A-1
I/O
Data inputs/Outputs or Address input.
26
E
I
Chip Enable.
28
G
I
Output Enable.
11
W
I
Write Enable.
12
RP
I
Reset/Block Temporary Unprotect.
15
RB
I
Ready/Busy Output.
47
BYTE
I
Byte/Word Organization Select
37
Vcc
---
Supply Voltage (3.0V)
27, 46
Vss
---
Ground.
10, 13, 14
NC
---
Not Connected Internally.
Pin No.
Pin Name
I/O
Pin Function
1
OUT
O
Output. OUT is the source of the P-channel MOSFET.
2
GND
---
Ground.
3
EN
I
Enable. The P-channel MOSFET turns on when EN is logic HIGH.
4
NC
---
No Connect. This pin is not internally connected.
5
GND
---
Ground.
6
IN
I
Input. IN is the drain of the P-channel MOSFET.
It is the supply input of the IC.
It is the supply input of the IC.
LC-26D44E/S/RU-BK/GY
5 – 19
14. IC8103 (VHIT3Z18AFG-1Q)
Single Link LCD Receiver
The LVDS is essentially a signaling method used for high-speed transmission of binary data over copper.
It uses a lower voltage swing than other transmission standards. This low voltage differential is what delivers higher data transmission speeds and
inherently greater bandwidth at lower power consumption.
inherently greater bandwidth at lower power consumption.
This new technology not only addresses the needs of today’s high performance data transmission application, but also the needs of future applica-
tion.
tion.
This LVDS receiver IP supports Single Link transmission between Host and Flat Panel Display. The receiver recovers the LVDS data and converts
into CMOS data. An on-chip PLL synchronizes the received clock with the parallel data and then all are transmitted to the parallel output port of the
receiver.
into CMOS data. An on-chip PLL synchronizes the received clock with the parallel data and then all are transmitted to the parallel output port of the
receiver.
Description:
• Supports Single Link (Single Input to Single Output) up to 135MHz dot clock for SXGA+ (input clock frequency: 25 to 135MHz)
• PLL requires no external components
• Clock strobe edge selectable
• Support 10-bit color
• Power down mode
Pin No.
Pin Name
I/O
Function Name
Pin No.
Pin Name
I/O
Function Name
1
PLLAVD
1.5V
E1AVDLIVC
141
SCLK
OUT
BT4VIC1
2
PLLAVS
GND
E1AVSLIVC
142
SDT
I/O
BD4THVIC1
3
VSSAGND45L
GND
Z7RSTAGND45L
143
vext1103
1.5V
SDRAMVDE1
4
VDDSAVCC4
3.3V
Z7RSTAVCC4
144
VDDC
1.5V
VDDC
5
VSSAGND45C
GND
Z7RSTAGND45C
145
RESET
IN
SMTCIF
6
VDDSAVCC5
3.3V
Z7RSTAVCC5
146
CMOS_IN
IN
IBUFDIF
7
BR0_M
OUT
Z7RSDST
147
OS_SEL
IN
TLCHTHDVIC1
8
BR0_P
OUT
Z7RSDST
148
OS_ON
IN
TLCHTHDVIC1
9
BR1_M
OUT
Z7RSDST
149
BANK_SEL
IN
TLCHTHDVIC1
10
BR1_P
OUT
Z7RSDST
150
TEMP[2]
IN
TLCHTHDVIC1
11
BR2_M
OUT
Z7RSDST
151
vgnd87
GND
SDRAMVSE
12
BR2_P
OUT
Z7RSDST
152
TEMP[1]
IN
TLCHTHDVIC1
13
BR3_M
OUT
Z7RSDST
153
TEMP[0]
IN
TLCHTHDVIC1
14
BR3_P
OUT
Z7RSDST
154
REV_MODE
IN
TLCHTHDVIC1
15
BCLK_M
OUT
Z7RSDST
155
HSCAN
IN
TLCHTHDVIC1
16
BCLK_P
OUT
Z7RSDST
156
VSCAN
IN
TLCHTHDVIC1
17
VDDSAVCC4
3.3V
Z7RSTAVCC4
157
vext1105
1.5V
SDRAMVDE1
18
VSSDGND1
GND
Z7RSTDGND1
158
VSS12
GND
VSS12
19
VDDCDVCC1
1.5V
Z7RSTDVCC1
159
SELLVDS
IN
TLCHTHUVIC1
20
VSSAGND45C
GND
Z7RSTAGND45C
160
SSCLK
I/O
BD8SCIF
21
VDDSAVCC5
3.3V
Z7RSTAVCC5
161
EXCLK
IN
IBUFIF
22
BG0_M
OUT
Z7RSDST
162
VDDC
1.5V
VDDC
23
BG0_P
OUT
Z7RSDST
163
VSSAGND1L
GND
Z7LVRAGND1L
24
BG1_M
OUT
Z7RSDST
164
RA_M
IN
Z7LVRXIO
25
BG1_P
OUT
Z7RSDST
165
RA_P
IN
Z7LVRXIO
26
BG2_M
OUT
Z7RSDST
166
RB_M
IN
Z7LVRXIO
27
BG2_P
OUT
Z7RSDST
167
RB_P
IN
Z7LVRXIO
28
BG3_M
OUT
Z7RSDST
168
RC_M
IN
Z7LVRXIO
29
BG3_P
OUT
Z7RSDST
169
RC_P
IN
Z7LVRXIO
30
VDDSAVCC4
3.3V
Z7RSTAVCC4
170
VDDAVDD1L
3.3V
Z7LVRAVDD1L
31
VSSDGND1
GND
Z7RSTDGND1
171
L_VDDPLL1
2.5V
Z7LVRVDDPLL1
32
VDDCDVCC1
1.5V
Z7RSTDVCC1
172
L_VSSPLL1
GND
Z7LVRVSSPLL1
33
VSSAGND45C
GND
Z7RSTAGND45C
173
L_VDDPLL2
2.5V
Z7LVRVDDPLL2
34
VDDSAVCC5
3.3V
Z7RSTAVCC5
174
L_VSSPLL2
GND
Z7LVRVSSPLL2
35
BB0_M
OUT
Z7RSDST
175
L_VDDD
1.5V
Z7LVRVDDD
36
BB0_P
OUT
Z7RSDST
176
L_VSSD
GND
Z7LVRVSSD
37
BB1_M
OUT
Z7RSDST
177
PVDDA1B
2.5V
Z7LVRVDDPLL1*1
38
BB1_P
OUT
Z7RSDST
178
PVDDA2B
2.5V
Z7LVRVDDPLL2*1
39
BB2_M
OUT
Z7RSDST
179
VDDS_L
3.3V
Z7LVRVDDS
40
BB2_P
OUT
Z7RSDST
180
PVSSA1B
GND
Z7LVRVSSPLL1*1
41
BB3_M
OUT
Z7RSDST
181
PVSSA2B
GND
Z7LVRVSSPLL2*1
42
BB3_P
OUT
Z7RSDST
182
VDDC_L
1.5V
Z7LVRVDDC
43
VDDCLCDVDDC
1.5V
Z7RSTVDDC
183
VDDAVDD2
2.5V
Z7LVRAVDD2
44
VSSLCDVSS2
GND
Z7RSTVSS2
184
VSSAGND2
GND
Z7LVRAGND2
45
VSSAGND45R
GND
Z7RSTAGND45R
185
VDDAVDD1R
3.3V
Z7LVRAVDD1R
LC-26D44E/S/RU-BK/GY
5 – 20
46
vgnd0
GND
SDRAMVSE
186
RCLKM
IN
Z7LVRXIO
47
vext10
1.5V
SDRAMVDE1
187
RCLKP
IN
Z7LVRXIO
48
LS_B
OUT
B4IF
188
RD_M
IN
Z7LVRXIO
49
SPB1
OUT
BT8IF
189
RD_P
IN
Z7LVRXIO
50
SPB2
OUT
BT8IF
190
RE_M
IN
Z7LVRXIO
51
VDDS
3.3V
VDDS
191
RE_P
IN
Z7LVRXIO
52
VSS12
GND
VSS12
192
VSSAGND1R
GND
Z7LVRAGND1R
53
REV
OUT
B4IF
193
VDDC
1.5V
VDDC
54
vext12
1.5V
SDRAMVDE1
194
CLKOUT
OUT
Z7DDRVO
55
GOE
OUT
B4IF
195
VDDS
3.3V
VDDS
56
GCK
OUT
B4IF
196
VCSV1
OUT
B4IF
57
GSP1
OUT
BT4IF
197
VCSV2
OUT
B4IF
58
GSP2
OUT
BT4IF
198
VCSV3
OUT
B4IF
59
GSLOP
OUT
B4IF
199
VCSV4
OUT
Z7DDRVO
60
VPOL
I/O
BD4CIF
200
VCSV_Z
OUT
B4IF
61
VDDC
1.5V
VDDC
201
VSS12
GND
VSS12
62
VSS12
GND
VSS12
202
SPA2
OUT
BT8IF
63
ROM256
IN
IBUFDIF
203
SPA1
OUT
BT8IF
64
MASTER
IN
IBUFDIF
204
LS_A
OUT
B4IF
65
vext13
1.5V
SDRAMVDE1
205
VDDS
3.3V
VDDS
66
vgnd2
GND
SDRAMVSE
206
VSSAGND45L
GND
Z7RSTAGND45L
67
EX_DT[0]
I/O
BD4CIF
207
VDDCLCDVDDC
1.5V
Z7RSTVDDC
68
EX_DT[1]
I/O
BD4CIF
208
VSSLCDVSS2
GND
Z7RSTVSS2
69
vext21
2.5V
SDRAMVDE2
209
FR0_M
OUT
Z7RSDST
70
vgnd3
GND
SDRAMVSE
210
FR0_P
OUT
Z7RSDST
71
vext147
1.5V
SDRAMVDE1
211
FR1_M
OUT
Z7RSDST
72
vgnd37
GND
SDRAMVSE
212
FR1_P
OUT
Z7RSDST
73
vext22
2.5V
SDRAMVDE2
213
FR2_M
OUT
Z7RSDST
74
EX_DT[2]
I/O
BD4CIF
214
FR2_P
OUT
Z7RSDST
75
VDDS
3.3V
VDDS
215
FR3_M
OUT
Z7RSDST
76
VSS12
GND
VSS12
216
FR3_P
OUT
Z7RSDST
77
EX_DT[3]
I/O
BD4CIF
217
FCLK_M
OUT
Z7RSDST
78
EX_DT[4]
I/O
BD4CIF
218
FCLK_P
OUT
Z7RSDST
79
EX_DT[5]
I/O
BD4CIF
219
VDDSAVCC4
3.3V
Z7RSTAVCC4
80
EX_DT[6]
I/O
BD4CIF
220
VSSDGND1
GND
Z7RSTDGND1
81
EX_DT[7]
I/O
BD4CIF
221
VDDCDVCC1
1.5V
Z7RSTDVCC1
82
EX_DT[8]
I/O
BD4CIF
222
VSSAGND45C
GND
Z7RSTAGND45C
83
EX_DT[9]
I/O
BD4CIF
223
VDDSAVCC5
3.3V
Z7RSTAVCC5
84
EX_DT[10]
I/O
BD4CIF
224
FG0_M
OUT
Z7RSDST
85
EX_DT[11]
I/O
BD4CIF
225
FG0_P
OUT
Z7RSDST
86
EX_DT[12]
I/O
BD4CIF
226
FG1_M
OUT
Z7RSDST
87
EX_DT[13]
I/O
BD4CIF
227
FG1_P
OUT
Z7RSDST
88
EX_DT[14]
I/O
BD4CIF
228
FG2_M
OUT
Z7RSDST
89
VDDS
3.3V
VDDS
229
FG2_P
OUT
Z7RSDST
90
VSS12
GND
VSS12
230
FG3_M
OUT
Z7RSDST
91
EX_DT[15]
I/O
BD4CIF
231
FG3_P
OUT
Z7RSDST
92
EX_SPIO
I/O
BD4CIF
232
VDDSAVCC4
3.3V
Z7RSTAVCC4
93
VDDC
1.5V
VDDC
233
VSSDGND1
GND
Z7RSTDGND1
94
VSS12
GND
VSS12
234
VDDCDVCC1
1.5V
Z7RSTDVCC1
95
EX_CLKI
IN
IBUFIF
235
VSSAGND45C
GND
Z7RSTAGND45C
96
EX_CLKO
OUT
B8IF
236
VDDSAVCC5
3.3V
Z7RSTAVCC5
97
EX_DT[16]
I/O
BD4CIF
237
FB0_M
OUT
Z7RSDST
98
EX_DT[17]
I/O
BD4CIF
238
FB0_P
OUT
Z7RSDST
99
EX_DT[18]
I/O
BD4CIF
239
FB1_M
OUT
Z7RSDST
100
EX_DT[19]
I/O
BD4CIF
240
FB1_P
OUT
Z7RSDST
101
EX_DT[20]
I/O
BD4CIF
241
FB2_M
OUT
Z7RSDST
102
EX_DT[21]
I/O
BD4CIF
242
FB2_P
OUT
Z7RSDST
103
VSS12
GND
VSS12
243
FB3_M
OUT
Z7RSDST
104
VDDS
3.3V
VDDS
244
FB3_P
OUT
Z7RSDST
105
EX_DT[22]
I/O
BD4CIF
245
VDDCLCDVDDC
1.5V
Z7RSTVDDC
106
EX_DT[23]
I/O
BD4CIF
246
VSSLCDVSS2
GND
Z7RSTVSS2
107
EX_DT[24]
I/O
BD4CIF
247
VDDSAVCC4
3.3V
Z7RSTAVCC4
108
EX_DT[25]
I/O
BD4CIF
248
R_VDDPLL1
2.5V
Z7RSTDDRV25
109
EX_DT[26]
I/O
BD4CIF
249
R_VDDPLL2
2.5V
Z7RSTDDRV25
Pin No.
Pin Name
I/O
Function Name
Pin No.
Pin Name
I/O
Function Name
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