Sharp AR-M165-207 (serv.man17) Service Manual ▷ View online
AR-M207 M165 M162 FLASH ROM VERSION UP PROCEDURE 12-6
6) PC side:
Check to confirm that the tree is displayed on [Special (MCU/IMC2/
Panel/ Facsimile)] of the integrated maintenance program. If the tree
is not displayed, check that the USB is properly connected and
select [Reconnect] again in the previous procedure of (5).
select [Reconnect] again in the previous procedure of (5).
7) PC side:
Double click [Special (MCU/IMC2/Panel/Facsimile)] on the main tree
items to extend the sub tree items, and select [Confirm version].
items to extend the sub tree items, and select [Confirm version].
8) Check to confirm that the display below is indicated.
Version confirming is completed with the following procedures:
•In version confirming, "**.**.**" means that connection is not made with
the MCU PWB or that download is not performed. (The above figure
shows the case where the FAX PWB is not installed.)
shows the case where the FAX PWB is not installed.)
•When download is completed, the version number is displayed such as
the MCU boot version and the MCU program version.
•The CPM and the SD-RAM size are displayed when the MCU/Panel
PWB is installed and the boot section operates normally.
[12]FLASHROM.fm 6 ページ ２００４年１１月１２日 金曜日 午後２時１９分
AR-M207 M165 M162 ELECTRICAL SECTION 13-1
[13] ELECTRICAL SECTION
1. Block diagram
Block Diagrams(Copier+SCANNEER+GDI+E-Sort+Duprex+USB2.0+FAX Model)
POWER SUPPLY
Scanner Unit
CCD PWB
12V
12V
Reg
A5V 3.3V
R
8bits(MSB/LSB)
B
5V
ADCCLK,SYNCH,
BSAMP,VSAMP
SDI,SCLK,LOAD,OBE
ł1, ł2, łTG, łTG2, łTG3
MODE
łRB, łCLB, ł1L
LVTTL
MCU-PWB
3.3V
IEEE 1284 I/F
USB I/F
Printer CLK(20.3094MHz)
3.3V
Download
Scanner CLK(48MHz)
A[19
1]
D[15
0]
A[19
1]
Shifter
MOTOR
8Kbyte
D[15
0]
Other Loads
MPFS,RRS,
SGS,SRRC,SPUS,SPPS,
Toner Motor
Mirror Motor
VFMCNT,VFM,MPFS,CPFS2,
CPFS1
Erther
CPU INTERRUPT
SPPD
CPU I/O
Pegasus2 main unit
I/F PWB
Pegasus ASIC
(296pin)
CPU
H8S/2321
(19.6608MHz)
I
E
E
E
1
2
8
4
U
S
B
1
1
LSU
EEPROM
SDRAM
Simp 16Mbyte
Dup 32Mbyte
Reset IC
SRAM
(2Mb(1Mb*2))
Driver
Flash ROM
(8Mbit)
AFE(AD9826 or AD9822)
C
D
S
A
G
C
M
P
X
AD
16bit
CCD Driver
CCFL
Lamp
Invertor
HOME
POSITION
SENSOR
CCD
(TCD2704)
CRUM
CPU CLK(19.6608MHz)
Software Reset
SSCG
SJMT0/1/2/3
Driver
LVC1284
PDIUSBP11AD
/POFF,HL,PR
FW
3.3V,5VEN,5V,24V
HVU
TC,GRID,MC,BIAS
COIN VENDOR/AUDITOR
/CV_COPY
/CV_COUNT,/CV_START,/CV_CA,
/CV_DPX,/CV_SIZE0,1,2,3
PMCLK(2078.74(Hz))
OPU_Reset
LCD PWB
TB62705CF
7seg LED
LED
5V
KEY MATRIX
INFO LAMP
UART
MHPS
SHIFTER
Driver
Sensor
SFTHP
/VIDEO
S/H
APCSTT
/SYNC
SPMT0/1/2/3
RSPF
Driver
SPFCLH,SPFGSOL
SPFPSOL,SPFRSOL
Sensor
Driver
Selector
L1,2
W0,1,2,3
/SPFCOVER,PAPER,
SPFOPEN,/SPFOUT
SPFMOTOR
PWM
12V,5V,3.3V
FAN
(Measures against
ozone)
24V
HC151
Image BUS (PI-Bus)
Image BUS (PO-Bus)
CLON
DUPLEX
Driver
2nd, 3rd, 4th cassettes
Feed SOL, Pick up SOL
Cassette detection,
Paper detection,
Paper pass detection,
Door detection
SELIN1,2,3
Y1
PSOL
FSOL
8
8
IMC2 PWB
OA982
DIMM SOCKET
SDRAM
Flash ROM
ISP1581
ADRS
Latch
P-Bus
JTAG
Image BUS (M-Bus)
16
FAX_Reset
UART
Video
HSYNC
LCD
(73dot x 119dot)
24V
FAX KEY PWB
FAX KEY
Document size unit
Document size unit
AR-NB3(Network box)
PCL
Network print & scan
PC
FAX-PWB UN
CPU
H8S/2321
(19.6608MHz)
Buzzer
SRAM
(1Mb)
Flash ROM
(4Mbit,8Mbit)
SSCG
Kanji font ROM
(Japan only)
CPU CLK(19.6608MHz)
Backlight (Green LED)
Job Separator
Driver
Sensor
DMT0/1/2/3
JOBS_FMT0/1/2/3
AC-Adaptor
Network Box PWB UN
ł(19.6608MHz)
KEY PWB
OC open/close
detection
UART
ES_Reset
USB2.0
High-speed
/MMD
/MMRDY
TM+,TM-
MM_AI0/Al1/PH_
MM_BI0/Bl1/PH_
PMD
Polygon
Motor
B/W
G
RTH DRST
Other Inputs
MainMotor
I/O ASIC
UART with FIFO
Expansion I/O port
Document size sensor
control
USB 2
(USB 2.0 / 1.1)
[13]ELECTRICALSECTION.fm 1 ページ ２００４年１１月１２日 金曜日 午後２時２１分
AR-M207 M165 M162 ELECTRICAL SECTION 13-2
2. Circuit descriptions
A. Main PWB (MCU)
(1) General
The MCU PWB is composed of:
• CPU peripheral sections which perform mechanical sequence control
and function job management
• Image process ASIC which performs image process, CCD control, LSU
control, and print control
• Motor control circuit
• Mechanical load, sensor I/O circuit
It controls the processes for copying, the transport loads, fusing, the
optical system, the operation panel, and the option PWB.
optical system, the operation panel, and the option PWB.
(2) CPU signal table (H8S/2321)
No.
SIGNAL
In/Out
DESCRIPTION
1
PG3/CS1
Out
ChipSelect for SRAM
2
PG4/CS0
Out
ChipSelect for ROM
3
Vss
GND
Ground
4
NC
GND
Ground
5
Vcc
3.3V
Power
6
PC0/A0
Pull-Up
Address Bus
7
PC1/A1
Out
Address Bus
8
PC2/A2
Out
Address Bus
9
PC3/A3
Out
Address Bus
10
Vss
GND
Ground
11
PC4/A4
Out
Address Bus
12
PC5/A5
Out
Address Bus
13
PC6/A6
Out
Address Bus
14
PC7/A7
Out
Address Bus
15
PB0/A8
Out
Address Bus
16
PB1/A9
Out
Address Bus
17
PB2/A10
Out
Address Bus
18
PB3/A11
Out
Address Bus
19
Vss
GND
Ground
20
PB4/A12
Out
Address Bus
21
PB5/A13
Out
Address Bus
22
PB6/A14
Out
Address Bus
23
PB7/A15
Out
Address Bus
24
PA0/A16
Out
Address Bus
25
PA1/A17
Out
Address Bus
26
PA2/A18
Out
Address Bus
27
PA3/A19
Out
Address Bus
28
Vss
GND
Ground
29
PA4/A20/IRQ4
Pull-Up
Address Bus
30
PA5/A21/IRQ5
In
EXT-PCB Wake Up Interrupt
31
PA6/A22/IRQ6
In
SPF Paper Detect Interrupt
32
PA7/A23/IRQ7
In
ASIC Interrupt
33
P67/IRQ3/CS7
In
Mirror Home Position Interrupt
34
P66/IRQ2/CS6
In
ASIC Interrupt
35
Vss
GND
Ground
36
Vss
GND
Ground
37
P65/IRQ1
In
Zero Cross Interrupt
38
P64/IRQ0
In
ASIC Interrupt
39
Vcc
3.3V
Power
40
PE0/D0
In/Out
Data Bus
41
PE1/D1
In/Out
Data Bus
42
PE2/D2
In/Out
Data Bus
43
PE3/D3
In/Out
Data Bus
44
Vss
GND
Ground
45
PE4/D4
In/Out
Data Bus
46
PE5/D5
In/Out
Data Bus
47
PE6/D6
In/Out
Data Bus
48
PE7/D7
In/Out
Data Bus
49
PD0/D8
In/Out
Data Bus
50
PD1/D9
In/Out
Data Bus
51
PD2/D10
In/Out
Data Bus
52
PD3/D11
In/Out
Data Bus
53
Vss
GND
Ground
54
PD4/D12
In/Out
Data Bus
55
PD5/D13
In/Out
Data Bus
56
PD6/D14
In/Out
Data Bus
57
PD7/D15
In/Out
Data Bus
58
Vcc
3.3V
Power
59
P30/TxD0
Out
CRUM I2C Bus Control
60
P31/TxD1
Out
For Debug
61
P32/RxD0
In/Out
12C Bus DATA
62
P33/RxD1
Option Cassette Detect Signal
63
P34/SCK0
Out
12C Bus Clock
64
P35/SCK1
In
USB Detect Signal
65
Vss
GND
Ground
66
P60/DREQ0/
CS4
Out
Not use
67
Vss
GND
Ground
68
Vss
GND
Ground
69
P61/TEND0/
CS5
In
Flash ROM Ready/Busy
70
P62/DREQ1
Out
Outconnect telephone control
71
P63/TEND1
Out
USB I/F Control
72
P27/PO7/
TIOCB5/TMO1
Out
Not use
73
P26/PO6/
TIOCA5/TMO0
Out
74
P25/PO5/
TIOCB4/TMCI1
Out
Power OFF Signal
75
P24/PO4/
TIOCA4/TMRI1
Print Start Signal
76
P23/PO3/
TIOCD3/TMRI0
Out
Duplex Motor Drive
77
P22/PO2/
TIOCC3/TMRI0
Out
Duplex Motor Drive
78
P21/PO1/
TIOCB3
Out
Duplex Motor Drive
79
P20/PO0/
TIOCA3
Out
Duplex Motor Drive
80
WDTOVF
Pull-Up
Watchdog Timer Over flow
81
RES
In
Reset Input
82
NMI
Pull-Up
NMI Interrupt
83
STBY
Pull-Up
Stand-by
84
Vcc
3.3V
Power
85
XTAL
19.6608MHz System Clock
86
EXTAL
19.6608MHz System Clock
87
Vss
GND
Ground
88
PF7/fai
Pull-Up
System Clock
89
Vcc
3.3V
Power
90
RF6/AS
Out
Software Reset Signal
91
RD
Out
Read Enable
92
HWR
Out
High Write Enable
93
PF3/LWR
Out
Low Write Enable
94
PF2/LCAS/
WAIT/BREQO
Out
151 Selector Signal
95
PF1/BACK
Out
151 Selector Signal
No.
SIGNAL
In/Out
DESCRIPTION
[13]ELECTRICALSECTION.fm 2 ページ ２００４年１１月１２日 金曜日 午後２時２１分
AR-M207 M165 M162 ELECTRICAL SECTION 13-3
96
PF0/BREQ
Out
151 Selector Signal
97
P50/TxD2/IRQ4
Out
IMC2 Status Transmission
98
P51/RxD2/IRQ5
In
IMC2 Status Reception
99
Vss
GND
Ground
100
Vss
GND
Ground
101
P52/SCK2/IRQ6
In
IMC2 Status Transmission
Enable
Enable
102
P53/ADTRG/
IRQ7/WAIT/
BREQO
Out
IMC2 Status Reception Ready
103
Avcc
3.3V
A/D Power
104
Vref
3.3V
A/D Reference
105
P40/AN0
In
Thermistor Analog Input
106
P41/AN1
In
SPF Wide Sensor
107
P42/AN2
In
151 Selector Input
108
P43/AN3
In
151 Selector Input
109
P44/AN4
In
151 Selector Input
110
P45/AN5
In
151 Selector Input
111
P46/AN6/DA0
In
Not use
112
P47/AN7/DA1
In
Analog Input(TC)
113
Avss
GND
Ground
114
Vss
GND
Ground
115
P17/PO15/
TIOCB2/TCLKD
Out
Scan stop Signal
No.
SIGNAL
In/Out
DESCRIPTION
116
P16/PO14/
TIOCA2
Out
Scan start Signal
117
P15/PO13/
TIOCB1/TCLKC
Out
Trans start Signal
118
P14/PO12/
TIOCA1
Out
Polygon Motor Clock
119
P13/PO11/
TIOCD0/TCLKB
Out
SPF Motor Drive
120
P12/PO10/
TIOCC0/TCLKA
Out
SPF Motor Drive/Mirror Motor
Step count
Step count
121
P11/PO9/
TIOCB0/DACK1
Out
SPF Motor Drive
122
P10/PO8/
TIOCA0/DACK0
Out
SPF Motor Dribe
123
MD0
GND
CPU Mode Control
Input(Mode4)
Input(Mode4)
124
MD1
GND
CPU Mode Control
Input(Mode4)
Input(Mode4)
125
MD2
Pull-Up
CPU Mode Control
Input(Mode4)
Input(Mode4)
126
PG0/CAS
Out
Not use
127
PG1/CS3
Out
ChipSelect for I/O ASI
128
PG2/CS2
Out
ChipSelect for ASIC
No.
SIGNAL
In/Out
DESCRIPTION
(3) Image process ASIC (HG73C141HFV)
a. General
The ASIC is composed of the three major blocks: the image process section, the print control section, and the I/F section.
•Image process section:
With image data from the CCD PWB in the operation mode determined by the register setup, shading, AE process, input
γ
correction, area separation,
filter process, resolution conversion, zoom process, output
γ
correction, binary conversion (error diffusion, dither method, simple binary conversion) are
performed.
•Print control section:
When copying, the image-processed data are outputted to the LSU according to the LSU writing timing. When scanning, the image data are made into
When copying, the image-processed data are outputted to the LSU according to the LSU writing timing. When scanning, the image data are made into
8bit width and outputted to the I/F section (USB).
•I/F section:
Controls the DRAM which is the image data buffer, and processes data send/receive between the USB I/F and the IEEE1284 I/F.
Controls the DRAM which is the image data buffer, and processes data send/receive between the USB I/F and the IEEE1284 I/F.
The ASIC is controlled by writing the operation mode and the necessary setup values of the operation mode into the ASIC control register before
starting each operation. (For ASIC Pin configuration, refer to the table at the end of this document.)
Scan start
CCD
PWB
PWB
Shading
CCD drive
AE
Resolution conversion,
Zooming, lmage
process circuit
Zooming, lmage
process circuit
Print data process circuit
DRAM control
PRINT control
DRAM
8MB or 16MB
8MB or 16MB
LSU
HSYNC
VSYNC
To CPU bus
ASIC
Image process section
I/F section
Print control section
ASIC control resistor
[13]ELECTRICALSECTION.fm 3 ページ ２００４年１１月１２日 金曜日 午後２時２１分
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