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AR-C200P   Rev.5 

1

3

 /

 

2.1

Main Board (TIG PWB)

Figure 2-2 provides the block diagram of the main control board (TIG PWB).

Figure 2-2

3

PU-CU

200

pin

C2516

EEPROM

V

ideo Data K, 

Y

, M, C

V

ideo I/F From PU

PU-CU I/F 

T

o C2 LSI

to PU   PU-CU Command I/F

to PU   Panel I/F

A

 [31:0]

SUB Bus 

A/D [31:0], Cont

[15:0]

SPD

[2]

[1]

[0]

SUB Bus

a Line 

Address. Cont

b Line 

Address. Cont

D [63:0]

[15:0]

[7:0]

D [63:0]

D [63:0]

D [63:0]

D

 [15:0]

Cont

Panel I/F From C2 LSI

3.3V

Reset IC

2.5V

1.8V

12V

3.3V

5V

2.5V

14.31818MHz

Crystal

 Resonator

M62733ML

(PU3V)

PST596

(PU12V)

PST596

(+5V)

internal

CPU CLK

setting Resister

PLL702-01

3.3V

Regulator

PPC

750cx

Core:1.8V

I/O:2.5V

2.5V

Regulator

CA1 LSI

MHM

2030-003

(uPD856

11N7)

Core:2.5V

I/O:3.3V

CPU I/O:2.5V

C2 LSI

MHM2031-002

DRCLK

3.3V

100MHz

RAMCLK

From 702

LV

C

161284

PLL102-5

33MHz

×

5

33MHz 3.3V 

×

4

33MHz 3.3V

USB

C

e

n

t

r

o

L60851

PCI

Slot

FPGA

for IDE

CENT

PCI

Reset

IDE

HDD

I/O 2.5V

74L

VC04

to each LSI

MPUCLK

2.5V

100MHz

CA1CLK

2.5V

100MHz

48MHz

 to USB

33MHz

33MHz

33MHz

Local

33MHz

48MHz

A,Cont

1.8V

Regulator

+

Flash

Mask 32bit 

×

2

ROM DIMM 

×

2

SDRAM DIMM 

×

3

SDRAMCLK

×

12

3.3V 100MHz

1

2

PCI BUS [31:0]

AR-C200P   Rev.5 

14/

  

(1)

CPU
The CPU is PowerPC750CXe, a 64-bit bus RISC processor, which inputs an 100-MHz CLK
(= BUS CLK), and operates at 450MHz that is 4.5 times the input.

(2)

Cache
PPC750Cxe has its cache only inside of it.
Speed:

Same as CPU Core CLK speed

Capacity:
Primary Cache:

32 K bytes in D-cache capacity, 32 K bytes in I-cache capacity

Secondary Cache: 256 K bytes

(3)

ROM
ROM is to be inserted into the two 168 pin DIMM slots.  The slot A is for program ROM and
the slot B is for Japanese kanji fonts.  The slot C is not assigned.

(4)

RAM
RAM is to be inserted into the three 168 pin DIMM slots.  The DIMMs must be fitted in
descending labeled type No. order into the slots 1, 3, 2 and 4.

SDRAM DIMM Specifications:

Speed:  PC133 or more
Capacity:  64/128/256/512 MB
Configuration:  Without parity.  Without ECC.  SPD information is required.

(5)

EEPROM
EEPROM, an 8-pin DIP package, is to be inserted into the IC socket.  The EEPROM is of 16
Kbits for 3.3V power supply, and settings for controlling the controller block are stored in it.

(6)

Flash ROM
A 4Mbyte flash ROM is surface-mounted on the TIG board.  The flash ROM is composed of
four 2048k-by-16bit chips, and fonts and macros can be stored in it.

(7)

Memory Control LSI (CAI)
A 696-pin BGA package ASIC made by NEC. The chip mainly controls a CPU I/F, memory,
video data compression and decompression, and a PU-video I/F.

(8)

Interface Control LSI (C2)
A BGA package ASIC made by Toshiba, which controls a PU command I/F, operator panel
I/F, IDE I/F, Centronics I/F, USB I/F, PCI I/F, EEPROM and a SPD (SDRAM DIMM) I/F.

(9)

IDE HDD
An IDE connector is surface-mounted on the board to which an IDE HDD assembled using
exclusive molds will be connected.  The IDE HDD is used for storing font data, spooling edited
video data and registering form data.

(10) PCI Bus Option

Two PCI I/F slots are provided for option board use.  The bus, which uses an Oki Data original
connector, can accept an Ethernet board.

(11) Host Interface

Standard:

Centronics two-way parallel I/F (IEEE-1284-compliant)
USB (USB1.1-compliant)

Additional Board: (connected to PCI BUS)

Ethernet Board

AR-C200P   Rev.5 

15/

  

Figure 2-3

The engine control block (PU) is controlled by the engine controller board (K71 PWB) which
consists of a CPU (MSM66Q577), general LSI chip, flash ROM, EEPROM, pulse motor drivers and
a video memory (see Figure 2-3).

(1)

CPU
This, a 16-bit CPU with an AD converter (OKI MSM66Q577), controls the entire system.

(2)

General LSI

2.2

Engine Controller Board (K7N PWB)

OPTION TRAY

INT

28MHz

CPU

MSM66Q577

FLASH

MCON

LSI

SRAM

EEPROM

CONTROL
PANEL

MOTOR
DRIVER

PULSE
MOTOR *9

GEARED
MOTOR

CLUTCH

LED HEAD (K)

LED HEAD (Y)

LED HEAD (M)

LED HEAD (C)

PU FAN
FUSER FAN

ID, BELT, 
FUSER
CHECKS

CLOCK
GENERATOR

DCON

LSI

MOTOR
DRIVER

CLK

RESET

DUPLEX

PAPER SIZE

STACKER FULL

CU

SDRAM

SDRAM

PAPER THICKNESS
SENSOR

COROR REGISTRATION
SENSOR

COVER OPEN
(UPPER, STACKER, RIGHT SIDE)

1ST TRAY SENSORS
(PAPER END, PAPER NEAR END)

PAPER FEED SYSTEM SENSORS
(PAPER FEED, PAPER
REGISTRATION, EJECT)

MT SENSORS
(STAGE POSITION, PAPER END)

DISPOSAL TONER SENSOR

HEAT ROLLER TEMP

OHP

TEMPATURE
HUMIDITY

HEAD TEMP

DENSITY

ANALOG

SW

32MHz

HIGH VOLTAGE POWER
SUPPLY SERIAL INTERFACE

This LSI (UPD65454GD-241-LML, UPD65946GD-137-LML), which is contained in the
printer engine control block, incorporates 4 megabits of video memory and has functions
such as engine-controller interfacing, LED interfacing, motor control, sensor input, video
memory control, main scan color misalignment correction, skew correction and high-voltage
power supply control.

AR-C200P   Rev.5 

16/

  

Output Voltage

Use for

+5 V

LED head

+5 V

Logic circuit power supply, PU CPU

+34 V

Motor, drive voltage and power supply voltage for high voltage power supply

+12 V

High voltage power supply, Media Thickness Sensor power supply

(2)

High Voltage Power Unit

This circuit generates the following voltages of not less than +34V, which are required for
electrophotographic process, according to control sequences from the controller board.

2.3

Power Units

There are a low voltage power unit consists of an AC filter circuit, low voltage power circuit and
heater driver circuit, and a high voltage power unit organizes a high voltage power circuit.

(1)

Low Voltage Power Unit

This circuit generates the following voltages:

(3)

MCON LSI
This LSI is used for inport  of SENSORs and the cntrols of Pulse Motors,Cluches,FANs and
High Voltage Power Suply.

(4)

Flash ROM
The flash ROM (29F800-70) is of 8-Mbits, and PU programs are stored in it.

(5)

EEPROM
The EEPROM (NM93C66N-NW) is of 4-Kbits, and mounted on the board with an IC socket.
Correction values are stored in it.

(6)

Pulse Motor Driver
The pulse motor driver (A2919SLBTR, A3955SLBTR,MTD2005) drives the eight pulse
motors to revolve the ID and transport media.

(7)  SRAM

This SRAM (628100LG-55L) is used as working memory of the CPU.

(8)  SDRAM

This SRAM (56V16160T) is used as data memory of the DCON LSI.

Output

Voltage

Use for

Remark

CH

-1000V  to 1.4KV+/-50V

Voltage to charging roller

DB

-50 to -300V/ +300V

Voltage to developing roller

SB

-300V to -450V/ 0V

Voltage to toner supplying roller

TR

C: 0KV to 7KV

Voltage to transfer roller

Variable

K,Y,M:  0KV to 6KV