Sharp UP-X300 (serv.man45) Service Manual ▷ View online
UP-X300V
CIRCUIT DESCRIPTION
4 – 3
3. PERIPHERAL CONTROLLER FOR POS (
III
)
1. OUTLINE
1-1. FUNCTION
Peripheral Controller for POS (III) (hereafter called PCPIII) uses Hita-
chi microprocessor H8S2138 and has the following functions:
• Magnetic card read and write control
• Clock control
• Clerk key I/F (Not for U.S. models)
• Drawer I/F
• General-purpose input port (x8 bit) and input/output port (x 8 bit) control
1-2. SYSTEM CONFIGURATION
1-3. DESCRIPTION OF FUNCTIONS
1-3-1. Interface with host
(1) Outline
The PCPIII sends and receives commands and data to and from the
host CPU through two host interfaces which are classified by function
into the following two categories:
host CPU through two host interfaces which are classified by function
into the following two categories:
(2) Returned data sequence
The PCPIII executes commands from the host CPU on a multitask operation
basis. There is a possibility that data are not returned to the CPU in the order
the PCPIII has received. The order of data should be identified by the identifi-
cation code contained in data to be returned from the PCPIII to the host CPU.
basis. There is a possibility that data are not returned to the CPU in the order
the PCPIII has received. The order of data should be identified by the identifi-
cation code contained in data to be returned from the PCPIII to the host CPU.
(3) Execution of commands
The addresses to which a command and data from the host CPU to the
PCPIII are different. Therefore, the PCPIII analyzes a command it has
received and waits for necessary data. It is thus necessary to send a com-
mand and data from the host CPU to the PCPIII as a matched pair.
It is not until the PCPIII analyzes a command and receives necessary data
that it executes the instruction.
If the number of data following a command is not as specified, the results is as
follows.
PCPIII are different. Therefore, the PCPIII analyzes a command it has
received and waits for necessary data. It is thus necessary to send a com-
mand and data from the host CPU to the PCPIII as a matched pair.
It is not until the PCPIII analyzes a command and receives necessary data
that it executes the instruction.
If the number of data following a command is not as specified, the results is as
follows.
(3)-1. If the number of data is insufficient:
• The PCPIII waits for data for good.
• The PCPIII ignores the instruction and the data whose number is
insufficient when it receives a new instruction before receiving the
necessary number of data.
necessary number of data.
(3)-2. If more than necessary number of data is received
The number of data required by a command is taken and the subsequent
data are ignored.
data are ignored.
(4) Host interface
(4)-1. Host CPU
3
PCP
III
Commands and data for devices sent from the host CPU to the PCPIII
are once stored in the host receive buffer. Commands and data stored
are then sent to the input buffer of each device.
If any one of the input buffers becomes full, the subsequent commands
and data sent from the host CPU to the PCPIII are stored in the host
receive buffer. If the host receive buffer is full, it no longer receives com-
mands and data from the host CPU.
are once stored in the host receive buffer. Commands and data stored
are then sent to the input buffer of each device.
If any one of the input buffers becomes full, the subsequent commands
and data sent from the host CPU to the PCPIII are stored in the host
receive buffer. If the host receive buffer is full, it no longer receives com-
mands and data from the host CPU.
(4)-2. PCP
III
3
host CPU
Data and status sent from each device to the host CPU are once stored in
the host send buffer and then sent to the host according to the read action
of the host CPU.
If data and status sent from each device to the host CPU cannot be stored
because the host CPU does not read the content of the host send buffer,
the processing of a command given from the host CPU is suspended in
principle. For this reason, if sending of commands and data from the host
CPU to the PCPIII is continued, the host receive buffer becomes full, mak-
ing it impossible to receive commands and data any further.
the host send buffer and then sent to the host according to the read action
of the host CPU.
If data and status sent from each device to the host CPU cannot be stored
because the host CPU does not read the content of the host send buffer,
the processing of a command given from the host CPU is suspended in
principle. For this reason, if sending of commands and data from the host
CPU to the PCPIII is continued, the host receive buffer becomes full, mak-
ing it impossible to receive commands and data any further.
1-3-2. Magnetic card
Three tracks of data can be read simultaneously and 1 track of data can be
written.
The room key card of magnetic stripe record type (Miwa Lock) is the JIS-II
type (JBA), but the start code of the JIS-type's second track (ABA) or the JIS-I
type's first track (JATA) is recorded at the beginning of the magnetic stripe.
As a result, when the start code is automatically identified by the controller,
data of the JIS II type cannot be read. Therefore, a special measure for the
JIS II type has been taken instead of performing automatic identification of the
start code.
To avoid this problem, the magnetic card will be decoded by the host CPU.
Therefore, bit data received by the PCPIII will be sent to the host CPU as it is.
In addition, written data will also be sent from the host CPU to the PCPIII as
bit data. This makes it possible to support any type of magnetic stripe record-
ing. It will also be possible to analyze read errors of a demagnetized magnetic
card.
written.
The room key card of magnetic stripe record type (Miwa Lock) is the JIS-II
type (JBA), but the start code of the JIS-type's second track (ABA) or the JIS-I
type's first track (JATA) is recorded at the beginning of the magnetic stripe.
As a result, when the start code is automatically identified by the controller,
data of the JIS II type cannot be read. Therefore, a special measure for the
JIS II type has been taken instead of performing automatic identification of the
start code.
To avoid this problem, the magnetic card will be decoded by the host CPU.
Therefore, bit data received by the PCPIII will be sent to the host CPU as it is.
In addition, written data will also be sent from the host CPU to the PCPIII as
bit data. This makes it possible to support any type of magnetic stripe record-
ing. It will also be possible to analyze read errors of a demagnetized magnetic
card.
Function
Interface
Host interrupt signal
Magnetic card
Host interface ch1
HiRQ12
Other than above
Host interface ch2
HiRQ11
Host CPU
PCPIII
Instruction for device 1
3
Instruction for device 2
3
1 Data returned to device 2
1 Data returned to device 1
PCP
III
䉟
RST
VCC
/RES
8
Drawer
Drawer
Power supply
Host CPU
H
o
st
in
te
rf
a
c
e
H
o
st
in
te
rf
a
c
e
Charge/discharge
control IC [BC]
Clerk key
S
y
n
c
h
ron
ou
s s
e
ri
a
l
S
y
n
c
h
ron
ou
s s
e
ri
a
l
S
y
n
c
h
ron
ou
s s
e
ri
a
l
Magnetic card device
Clock
General-purpose
I/O port
Host interface
Host
send
buffer
Host
receive
buffer
Device 1
Device 2
Device 3
Device 4
UP-X300V
CIRCUIT DESCRIPTION
4 – 4
PIN TABLE
Here is the pin table for the PCPIII
I
HOST INTERFACE
Bus control
No.
Function
Remarks
I/O
1
/RES
Input
2
XTAL
3
EXTAL
4
MD1
Input
5
MD0
Input
6
NMI
Input
7
/STBY
Input
8
VCC2
9
MCR_RCP1
SCK0
Input
10
MCR_RDD1#
RxD0
Input
11
MCR_DiN1#
TxD0
Output
12
VSS
13
B-D1
P97
I/O
14
B-D0
P96
I/O
15
/CS1
Input
16
/IOW
Input
17
/IOR
Input
18
MCR_CSL1#
IRQ0#
Input
19
MCR_CLS2#
IRQ1#
Input
20
MCR_CLS3#
IRQ2#
Input
21
Pio0
P60
22
Drawer1 IN
P61
Input
23
Drawer1 OUT
FTOA
Output
24
MCR_RWC1#
P63
Output
25
MCR_WTS1
P64
Input
26
Drawer2 IN
P65
Input
27
Drawer2 OUT
FTOB
Output
28
/B-SEL
P67
Output
29
AVCC
30
MCR_0
P70
Input
31
MCR_1
P71
Input
32
Pi2
P72
Input
33
Pi3
P73
Input
34
Pi4
P74
Input
35
Pi5
P75
Input
36
Pi6
P76
Input
37
/B-ACK
P77
Input
38
AVSS
39
LED_PWR#
P40
Output
40
MCR_RDD3#
RxD2
Input
41
MCR_RCP3
SCK2
Input
42
HIRQ11
Output
43
Pio1
P44
I/O
44
HIRQ12
Output
45
Pio2
P46
I/O
46
Pio3
P47
I/O
47
VCC1
48
Clerk DATA7
P27
Input
49
Clerk DATA6
P26
Input
50
Clerk DATA5
P25
Input
51
Clerk DATA4
P24
Input
52
Clerk DATA3
P23
Input
53
Clerk DATA2
P22
Input
54
Clerk DATA1
P21
Input
55
Clerk DATA0
P20
Input
56
VSS
57
Alarm_CLK
P17
Output
58
Alarm_DATA
P16
I/O
59
Alarm_CE
P15
Output
60
Pio4
P14
I/O
61
Pio5
P13
I/O
62
Pio6
P12
I/O
63
Pio7
P11
I/O
64
/B-STB
P10
Output
65
HDB0
I/O
66
HDB1
I/O
67
HDB2
I/O
68
HDB3
I/O
69
HDB4
I/O
70
HDB5
I/O
71
HDB6
I/O
72
HDB7
I/O
73
VSS
74
HA0
Input
75
/CS2
Input
76
Pi0
P82
Input
77
Pi1
P83
Input
78
Drawer-IN
IRQ3#
Input
79
MCR_RDD2#
RxD1
Input
80
MCR_RCP2
SCK1
Input
Host CPU side
Direction of
data flow
Type
PCPIII side
/CS1 /CS2 HA0 /WR
/RD
Host CPU
PCP III
Name
Abb
R/W
0
1
0
0
1
3
Data
Input
register1
IDR1
R
0
1
1
0
1
3
Command
0
1
0
1
0
1
Data
Output
register
ODR
W
R
0
1
1
1
0
3
Status
Status
register1
STR1
W
R
1
0
0
0
1
3
Data
Input
register2
IDR2R
R
1
0
1
0
1
3
Command
1
0
0
1
0
1
Data
Output
register2
SODR
2
W
R
1
0
1
1
0
1
Status
Status
register2
STR2
R
W
No.
Function
Remarks
I/O
UP-X300V
CIRCUIT DESCRIPTION
4 – 5
REGISTER
Input data registers 1/2 (ODR1/2)
This is an 8-bit read/write enable register for the PCPIII and 8-bit read-
only register for the host CPU.
The initial value is undefined when the system is reset or in the stand-by
mode.Register
Output data registers 1/2 (ODR1/2)
This is an 8-bit read/write enable register for the PCPIII and 8-bit read-
only register for the host CPU.
The initial value is undefined when the system is reset or in the stand-by
mode.
STATUS REGISTER 1/2 (STR1/2)
This shows the status of host interface processing.
Error (ERR)
This indicates that the main routine of the PCPIII is destroyed and the
loader of the boot block A or B waits for loading of write/erase control
program.
Command/data (C/D)
When the host CPU writes data to IDR, the status of HA0 is written and
whether the content of IDR is data or command is identified.
Ready/Busy (R/B)
This register indicates that the PCPIII is performing internal processing
and cannot receive any command from the host.
The bit becomes 0 when:
• The PCPIII is initialized after turned on
• The PCPIII does not want to receive any command (data) from the
hostor any reason although the input data register full (IBF) is 0.
Input data register full (IBF)
When the host CPU writes data in the IDR, the IBF bit is set to 1. This
becomes a factor for internal interruption against the PCPIII.
When the PCPIII reads data from the IDR, the IBF bit is cleared to 0.
Data read from the IDR is once stored in the host receive buffer com-
posed of the ring buffer.
posed of the ring buffer.
If the host receive buffer is full, IBF interruption should be inhibited and
any command from the host should not be received.
Output data register full (OBF)
When the PCPIII writes ODR, the OBF bit is set to 1.
When the host CPU read ODR, the OBF bit is cleared to 0.
4. UP-X300 I/O DESCRIPTION.
4-1. I/O ADDRESSES
Bit
:
7
6
5
4
3
2
1
0
IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0
Initial value
:
---
---
---
---
---
---
---
---
PCPIII
:
R
R
R
R
R
R
R
R
Host CPU
:
W
W
W
W
W
W
W
W
Bit
:
7
6
5
4
3
2
1
0
IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0
Initial value :
---
---
---
---
---
---
---
---
PCPIII
:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Host CPU
:
R
R
R
R
R
R
R
R
Bit
:
7
6
5
4
3
2
1
0
IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0
Initial value :
---
---
---
---
---
---
---
---
PCPIII
:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Host CPU
:
R
R
R
R
R
R
R
R
0 : PCPIII operates normally
1 : Waits for loading of write/erase control program
0 : The content of input data register (IDR1/2) is data
1 : The content of input data register (IDR1.2) is a command.
0
: PCPIII is busy and cannot receive commands from host.
1
: PCPIII is ready for receiving commands from host.
0
: [Clear condition] PCPIII reads IDR.
1
: [Set condition] Host CPU writes IDR.
0 : [Clear condition] Host CPU read ODR.
1 : [Set condition] PCPIII writes ODR.
1 : [Set condition] PCPIII writes ODR.
ch
I/O address
R/W
Type
Register
Interruption
Host interruption
Control device
1
7F0h
R
Data
Output register 1 (ODR1)
HiRQ12
iRQ15
Magnetic card Command
W
Data
Output register 1 (iDR1)
7F1h
R
Status
Status register 1 (STR1)
W
Status
Input register 1 (DR1)
2
7F2h
R
Data
Output register 2 (ODR2)
HiRQ11
iRQ15
Other than others
W
Data
Output register 2 (iDR2)
7F3h
R
Status
Status register 2 (STR2)
W
Command
Input register 2 (DR2)
UP-X300V
CIRCUIT DESCRIPTION
4 – 6
4-2. GENERAL-PURPOSE PORTS
4-2-1.Input ports
The program identifies the model name according to the model identification
numbers 0 - 3. By using this function, the following functions can be added.
numbers 0 - 3. By using this function, the following functions can be added.
• Software that runs only on the said model.
• Security that uses data encoded only by the said model.
4-2-2. I/O ports
(1) 5V1
Controls the supply of +5V output to COM2.
(2) 5V2
Controls the supply of +5V output to the customer display.
4-3. CLOCK
RICHO real time clock RV5C339A. The alarm function is not used.
4-4. BC
The charge/discharge control function of the Nickel-hydrogen battery is
not used.
not used.
4-5. SERIAL I/F
With a special program, it is possible to write PCPIII firmware through the
COM1.
COM1.
5. FUNCTIONAL SPECIFICATIONS
5-1. OUTLINE
This MCU is a touch panel controller which can be operated as the
standard HID under the USB host controller. It supports a 4-wire and 7-
wire resistance film touch panels.
It provides 3 buttons (left, right and center), scroll buttons (four direc-
It provides 3 buttons (left, right and center), scroll buttons (four direc-
tions), and 13-bit absolute coordinates for the USB host. Disconnect is
emulated by detecting the Low level/edge of the USB Disable signal.
After disconnecting by the Low level edge, Connect is emulated by
After disconnecting by the Low level edge, Connect is emulated by
detecting the High level edge.
This MCU does not have a correction function. An application including
correction function is installed by installing a special device driver to the
correction function is installed by installing a special device driver to the
said OS.
5-2. CONFIGURATION
The shaded part in the above sketch indicates the MCU.
For detail of the diagram, see the circuit diagram C1NC41120-0015.
Note that the specified function of the MCU is best obtained using our
Note that the specified function of the MCU is best obtained using our
genuine device driver.
5-3. PIN ARRANGEMENT AND FUNCTION
5-3-1.Pin arrangement diagram (7-wire type)
Pin Function
Pi0
Model identification 0
Pi1
Model identification 1
Pi2
Model identification 2
Pi3
Model identification 3
Pi4
Pi5
Pi6
Model identification
Model name
3
2
1
0
UP-X500
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Pin
Function
I/O
Pio0
5V1
Output
Pio1
Reserved (5V2)
Output
Pio2
Pio3
Pio4
Pio5
Pio6
Pio7
1 : Does not supply power
0 : Supplies power
1 : Does not supply power
0 : Supplies power.
MCU
M37534
10bit ADC
USB I/F
Application
(Correction tool, user mode driver, control panel)
(Correction tool, user mode driver, control panel)
USB driver
(Windows98/ME/
Win2K/WinXP)
Pen operation
Jumper wire
External
signal wire
signal wire
4-wire panel
EP0
EP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
< D+
< D-
< Button Middle
< Button Right
< Button Left
< PSW0
< PSW2
< PSW1
< PSW4
< PSW3
< USB Vrefout
< Module Disable
< JPMODE
< Wheel Down
< Wheel Up
< OS1
< OS2
< OS3
< D-
< Button Middle
< Button Right
< Button Left
< PSW0
< PSW2
< PSW1
< PSW4
< PSW3
< USB Vrefout
< Module Disable
< JPMODE
< Wheel Down
< Wheel Up
< OS1
< OS2
< OS3
Wheel Right >
Wheel Left >
CNTR0 >
PMSR >
EMSR0 >
EMSR1 >
EMSR2 >
EMSR3 >
EMSR1 >
EMSR2 >
EMSR3 >
PID1 >
PID2 >
PID3 >
PID2 >
PID3 >
V
REF
>
RESET
>
CNVss >
Vcc >
Xin >
Xout >
Vss >
Click on the first or last page to see other UP-X300 (serv.man45) service manuals if exist.