Sharp ER-A490 (serv.man4) Service Manual ▷ View online
III. HARDWARE DESCRIPTION FOR
ER-A5RS
1. General
The ER-A5RS is composed of the following blocks:
1) RS-232 receiver (75189A)
2) RS-232 driver (75188)
3) USART (MB89371A)
4) Gate array (OPC1: F256004PJ)
2. Block diagram
3. Description of main LSI
3-1. OPC1 (F256004PJ)
1) General description
The OPC1 is a gate array of integrated peripheral circuits of RS-
232/Simple IRC interface.
One chip of the OPC1 is equipped with four communication circuits.
(Three of them are for RS-232 only: UNIT 0 ~ 2, one is for selection of
simple IRC/RS-232: UNIT 3)
The ER-A5RS uses UNIT0 (RS-232 interface) and UNIT7 (RS-232
interface).
232/Simple IRC interface.
One chip of the OPC1 is equipped with four communication circuits.
(Three of them are for RS-232 only: UNIT 0 ~ 2, one is for selection of
simple IRC/RS-232: UNIT 3)
The ER-A5RS uses UNIT0 (RS-232 interface) and UNIT7 (RS-232
interface).
UNIT NO.
Purpose
ER-A5RS
UNIT0
RS-232
Used.
UNIT1
RS-232
Used.
UNIT2
RS-232
Not used.
UNIT3
RS-232/Simple IRC
Not used.
Each UNIT of the OPC1 has the following functions:
1
Timer function
Used for the timer between characters in data reception.
Used for the timer between characters in data reception.
2
Address decode
USART chip select output and own select.
USART chip select output and own select.
3
Interruption control
RSRQ, TRRQ output using outputs from USART (TRNRDY,
TRNEMP, RCVRDY, BRK) and RS-232 control signals (CI, CTS,
CD) as interruption factors.
(For the simple IRC, TRNEMP is excluded.)
RSRQ, TRRQ output using outputs from USART (TRNRDY,
TRNEMP, RCVRDY, BRK) and RS-232 control signals (CI, CTS,
CD) as interruption factors.
(For the simple IRC, TRNEMP is excluded.)
*
RSRQ:
TRRQ(Not used):
TRRQ(Not used):
For RS-232
For simple IRC
For simple IRC
4
Simple IRC send/receive control (UNIT3 only) : Not used
2) Pin configuration
CS1,CS2
A0~A5
R,W
RDO,WRO
DB0~7
OPTCS
INT (
✽
)
D0~D7
RES
RES,POFF
CLOK
RSRQ,TRQ1
AB0,1
DCD1,2 CI1,2
RCVDT1,2 CTS1,2
USART
DSR1,2
RS-232
Reciever
DTR1,2 TRNDT1,2
CD1,2 CI1,2
RD1,2 CS1,2
DR1,2
ER1,2 SD1,2
RS-232
Driver
RS1,2
Power
supply
circuit
+12V
-12V
RTS1,2
OPC1
PX
+24V
INT (
✽
): TRNRDY1,2 RCVRDY1,2 TRNEMP1,2 BRK1,2
CS3
CS2
TRNEMP3
BRK3
TRANDY3
RCVRDY3
RXDATA0
TRCK
RES
OPTCS
D0
D1
D2
D3
GND
D4
D5
D6
D7
RSRQ
A0
A1
A2
A3
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
T
RNE
M
P
2
CI
3/
P
2I
TRNRDY
2
RCV
DT2
SL
21
SL
20
SL
32
SL31
X1
X2
GN
D
VC
C
CD2
CI
2
CT
S
2
US
IC
H
TRRQ
TR
V
CT
S
0
CD
0
SL0
0
SL01
SL
02
SL
10
SL11
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
A5
PO
F
F
TRQ
1
WR
O
RDO
CS
1
AB
1
R
AB0
CS
0
W
CD3
/P
0
VC
C
GN
D
RC
V
D
T3
TX
E
CTS
3/
P
1
RT
S
1
CI
1
CD1
CTS
1
CI
0
RT
S
0
PX
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
SL12
RCVRDY2
RCVDT1
RCVRDY1
TRNRDY1
BRK1
DB7
DB6
DB5
DB4
GND
DB3
DB2
DB1
DB0
TRNEMP1
TRNRDY0
RCVDT0
RCVRDY0
TRNEMP0
BRK0
SL30
XOUT
SL22
RES
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
OPC1
F256004PJ
TR
Q
2
3 – 1
3) Block diagram
D7
D6
D5
D4
D3
D2
D1
D0
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
Data bus buffer
WRO
RDO
RES
W
R
RES
Read/write
control
control
A5
A4
A3
A2
A1
A0
SL00
CS0
Decorder
control
control
SL01
SL02
SL10
SL11
SL12
SL20
SL21
SL22
SL30
SL31
SL32
TRV
USICH
CS3
CS2
CS1
Chanel
sel
ect
cont
ro
l
CHSL
PX
TO/FROM USART
RX
D
A
T
A
0
TX
E
X1
X2
XO
U
T
TB
CK
Inline
cont
cont
OCS
TCR0
Timer0 control
Timer0
RCVDT0
TCR1
Timer1 control
Timer1
RCVDT1
TCR2
Timer2 control
Timer2
RCVDT2
TCR3
Timer3 control
Timer3
RCVDT3
RTS CNT
RTS1
RTS0
PO
F
F
RS
R
Q
T
RRQ
TR
Q
1
TR
Q
2
Power
supply
cont.
supply
cont.
RCVRDY3
RCVRDY2
RCVRDY1
RCVRDY0
TRNEMP3
TRNEMP2
TRNEMP1
TRNEMP0
Interrupt control
CI
0
CI
1
CI
2
CI
3/
P
2I
CD0
CD1
CD2
CD
3/
P
0
CT
S
0
CT
S
1
CT
S
2
CT
S
3
/P
1
BR
K
0
BR
K
1
BR
K
3
T
R
NRDY
0
T
RNRDY
1
T
RNRDY
2
T
RNRDY
3
AB1
AB0
3 – 2
4) Pin description
OPC1 pin table
The signals marked with "-" at the end are LOW active signals. Example: "CS1-" = "CS1"
No.
Pin No.
Pin name
I/O
Pin
ER-A5RS
Description
1
80
SL00
I
ICU
SL00
RS-232/UNIT0 channel select
2
79
SL01
I
ICU
SL01
3
78
SL02
I
ICU
SL02
4
77
SL10
I
ICU
SL10
RS-232/UNIT1 channel select
5
76
SL11
I
ICU
SL11
6
75
SL12
I
ICU
SL12
7
95
SL20
I
ICU
GND
RS-232/UNIT2 channel select
8
96
SL21
I
ICU
GND
9
52
SL22
I
ICU
GND
10
54
SL30
I
ICU
GND
RS-232/UNIT3 channel select
11
93
SL31
I
ICU
GND
12
94
SL32
I
ICU
GND
13
36
CS0-
O
O
CS1-
RS-232 USART chip select
14
32
CS1-
O
O
CS2-
15
2
CS2-
O
O
NC
16
1
CS3-
O
O
NC
RS-232/INLINE USART chip select
17
81
CD0-
I
IS
DCD1-
RS-232 control signal CD- input
18
46
CD1-
I
IS
DCD2-
19
88
CD2-
I
IS
GND
20
38
CD3-/P0-
I
IS
GND
RS-232 CD-/INLINE P0-
21
82
CTS0-
I
IS
CTS1-
RS-232 control signal CTS- input
22
47
CTS1-
I
IS
CTS2-
23
86
CTS2-
I
IS
GND
24
43
CTS3-/P1-
I
IS
GND
RS-232 CTS-/INLINE P1-
25
48
CI0-
I
IS
CI1-
RS-232 control signal CI- input
26
45
CI1-
I
IS
CI2-
27
87
CI2-
I
IS
GND
28
99
CI3-/P2I
I
IS
GND
RS-232 CI-/INLINE P2I
29
55
BRK0
I
ISC
BRK1
RS-232 USART BREAK signal
30
70
BRK1
I
ISC
BRK2
31
27
POFF-
I
IS
POFF-
POFF signal (LOW: P-OFF, HIGH: P-ON)
32
4
BRK3
I
IS
GND
RS-232/INLINE USART BREAK signal
33
57
RCVRDY0
I
ISC
RCVRDY1
RS-232 USART RCVRDY signal
34
72
RCVRDY1
I
ISC
RCVRDY2
35
74
RCVRDY2
I
ISC
GND
36
6
RCVRDY3
I
IS
GND
RS-232/INLINE USART RCVRDY signal
37
59
TRNRDY0
I
ISC
TRNRDY1
RS-232 USART TRNRDY signal
38
71
TRNRDY1
I
ISC
TRNRDY2
39
98
TRNRDY2
I
ISC
GND
40
5
TRNRDY3
I
IS
GND
RS-232/INLINE USART TRNRDY signal
41
56
TRNEMP0
I
ISC
TRNEMP1
RS-232 USART TRNEMP signal
42
60
TRNEMP1
I
ISC
TRNEMP2
43
100
TRNEMP2
I
ISC
GND
44
3
TRNEMP3
I
IS
GND
RS-232/INLINE USART TRNEMP signal
45
58
RCVDT0
I
ISC
RCVDT1
RS-232 RCVDT signal (LOW: TIMER START)
46
73
RCVDT1
I
ISC
RCVDT2
47
97
RCVDT2
I
ISC
GND
48
41
RCVDT3
I
IS
GND
RS-232/INLINE RCVDT signal
49
20
RSRQ-
O
3S
RSRQ-
RS-232 IRQ- signal
50
83
TRV-
I
ISC
+5V
INLINE YES/NO
51
7
RXDATA0
O
O
NC
INLINE RXDATA OUT
52
42
TXE
O
O
NC
INLINE TRNS ENABLE
53
84
TRRQ-
O
3S
NC
INLINE IRQ- signal
54
28
TRQ1-
O
3S
TRQ1
TIMER IRQ signal (RS-232)
3 – 3
No.
Pin No.
Pin name
I/O
Pin
ER-A5RS
Description
55
29
TRQ2-
O
3S
NC
TIMER IRQ signal (INLINE)
56
11
D0
I/O
IOU
D0
DATA BUS (MAIN)
57
12
D1
I/O
IOU
D1
58
13
D2
I/O
IOU
D2
59
14
D3
I/O
IOU
D3
60
16
D4
I/O
IOU
D4
61
17
D5
I/O
IOU
D5
62
18
D6
I/O
IOU
D6
63
19
D7
I/O
IOU
D7
64
61
DB0
I/O
IOU
DB0
DATA BUS (USART)
65
62
DB1
I/O
IOU
DB1
66
63
DB2
I/O
IOU
DB2
67
64
DB3
I/O
IOU
DB3
68
66
DB4
I/O
IOU
DB4
69
67
DB5
I/O
IOU
DB5
70
68
DB6
I/O
IOU
DB6
71
69
DB7
I/O
IOU
DB7
72
21
A0
I
I
A0
ADDRESS BUS (MAIN)
73
22
A1
I
I
A1
74
23
A2
I
I
A2
75
24
A3
I
I
A3
76
25
A4
I
I
A4
77
26
A5
I
I
A5
78
10
OPTCS-
I
I
OPTCS-
OPTION CHIP SELECT (from MAIN)
79
31
RDO-
I
I
RDO-
READ signal (from MAIN)
80
30
WRO-
I
I
WRO-
WRITE signal (from MAIN)
81
9
RES-
I
IS
RES-
RESET signal (from MAIN)
82
34
R-
O
O
R-
READ signal (To USART)
83
37
W-
O
O
W-
WRITE signal (To USART)
84
51
RES
O
O
RES
RESET signal (To USART)
85
92
X1
O
X1
Oscillation circuit
86
91
X2
I
X2
87
53
XOUT
O
O
XOUT
Clock for USART
88
8
TRCK
O
O
NC
T/R clock for 1CH USART
89
35
AB0
O
O
AB0
Address bus for USART
90
33
AB1
O
O
AB1
91
85
USICH
I
ISC
GND
UNIT3 USART 1CH/2CH select
92
50
PX
O
PX
Power source clock
93
39
VCC
+5V
94
89
VCC
+5V
95
15
GND
GND
96
40
GND
GND
97
65
GND
GND
98
90
GND
GND
99
49
RTS0-
O
O
RTS1-
RS-232 control signal RTS- output
100
44
RTS1-
O
O
RTS2-
ICU : CMOS level input (internal pullup resistor)
O
O
: Output
IS
: TTL level input (internal schmit circuit)
ISC : CMOS level input (internal schmit circuit)
3S
3S
: Three state output
IOU : I/O port (internal pullup resistor)
3 – 4
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