Sharp ER-A490 (serv.man4) Service Manual ▷ View online
3-2. USART (MB89371A)
1) General
The MB89371A (Serial data transmitter/receiver, 2 units) is a versa-
tile-use interface LSI for communication lines, which is equipped with
two sets of equivalent units of the MB89251A (serial data transmit-
ter/receiver), the baud rate generating section, and the interruption
adjustment section.
It is positioned between the line Modem and the computer, and used
for serial/parallel conversion of data, data send/receive operation
check, and the synchronization mode selection according to the pro-
gram assignment.
The transmitter section converts parallel data into serial data, and
adds the parity bit, the start bit, and the stop bit to them, and transmits
them. In the synchronization mode, it transmits synchronization char-
acters during no transmission data period. In the advancement syn-
chronization mode, it allows selection of transmission clocks and
transmission baud rates.
The receiving section converts serial data into parallel data, and
checks parities to judge that data are properly transmitted.
In the synchronization mode, it detects synchronization characters
and makes synchronization of transmission/reception operations with
the transmitter side. In the advancement synchronization mode, it
allows selection of transmission clocks and reception baud rates.
The baud rate generating section generates clock pulse signals which
are used in transmission and reception and delivered through the
baud rate selecting section to the SDTR section.
It provides the loop back diagnostic function which crosses interface
lines of the Modem and loops transmission and reception signals,
facilitating the operation check.
tile-use interface LSI for communication lines, which is equipped with
two sets of equivalent units of the MB89251A (serial data transmit-
ter/receiver), the baud rate generating section, and the interruption
adjustment section.
It is positioned between the line Modem and the computer, and used
for serial/parallel conversion of data, data send/receive operation
check, and the synchronization mode selection according to the pro-
gram assignment.
The transmitter section converts parallel data into serial data, and
adds the parity bit, the start bit, and the stop bit to them, and transmits
them. In the synchronization mode, it transmits synchronization char-
acters during no transmission data period. In the advancement syn-
chronization mode, it allows selection of transmission clocks and
transmission baud rates.
The receiving section converts serial data into parallel data, and
checks parities to judge that data are properly transmitted.
In the synchronization mode, it detects synchronization characters
and makes synchronization of transmission/reception operations with
the transmitter side. In the advancement synchronization mode, it
allows selection of transmission clocks and reception baud rates.
The baud rate generating section generates clock pulse signals which
are used in transmission and reception and delivered through the
baud rate selecting section to the SDTR section.
It provides the loop back diagnostic function which crosses interface
lines of the Modem and loops transmission and reception signals,
facilitating the operation check.
Features
●
Two independent channels of SDTR.
●
Built-in baud rate generator which allows setting for each channel
●
External clock available
●
Internal clock output available.
●
Maskable interruption generating circuit
●
Two channels are assigned to different address spaces.
●
Baud rate DC ~ 240K baud (with external clocks)
●
Full duplex communication
●
Program assignment in synchronization mode
•
Data bit length: 5 - 8 bits
•
Character synchronization system: Internal synchronization,
external synchronization
external synchronization
•
Number of synchronized characters: Single character, double
characters
characters
•
Parity occurrence and check: parity valid/invalid
even parity, odd parity
●
Operations in the synchronization mode
•
Overrun error and parity error detection
•
Transmit/receive buffer state acknowledgment
•
Synchronization character detection
•
Automatic insertion of synchronization character
●
Program assignment function in the advancement synchronization
mode
mode
•
Data bit length: 5 ~ 8 bits
•
Stop bit length: 1, 1
1
⁄
2
, 2 bits
•
Baud rate: Transmission clock, reception clock x 1, x 1/16, x
1/64
1/64
•
Parity occurrence and check: Parity valid, invalid
Even parity, odd parity
●
Operations in the advancement synchronization mode
•
Detection of framing error, overrun error, parity error
•
Transmission/reception buffer state acknowledgment
•
Break characters detection
●
Error start bit detection
●
IBM Bi-sync system operation allowed.
●
Duplex buffer system in the transmission and the reception sec-
tions.
tions.
●
Loop back diagnostic functions
●
I/O signal level TTL compatible
●
Compatible with standard microprocessor in connecting pins and
signal timing.
signal timing.
●
Standard 42 pin plastic DIP, 48 pin plastic QFP
●
+5V single power source
2) Pin configuration
3) Block diagram
1
DB4
2
DB5
3
DB6
4
DB7
5
TRNCLK1
6
W
7
CS1
8
RSLCT0
9
R
10
RCVRDY1
11
RSLCT1
12
CS2
48
N
C
47
GN
D
46
R
C
V
D
T
1
45
D
B
3
44
D
B
2
4
3
O
PEN
42
D
B
1
41
D
B
0
40
V
C
C
39
R
C
V
C
L
K
1
38
N
C
3
7
DT
R1
36
RTS1
35
DSR1
34
RST
33
CLOCK
32
TRNDT1
31
TRNEMP1/ST1-1
30
CTS1
29
SYNC/BRK1
28
TRNRDY1
27
RCVCLK2
26
DTR2
25
RTS2
13
RC
V
D
T
2
14
NC
15
T
RNCL
K
2
16
RCV
RDY
2
17
TR
N
R
D
Y
2
18
SYN
C
/BR
K2
19
O
PEN
20
CT
S
2
21
T
R
N
E
M
P
2/
S
T
1-
2
22
TR
N
D
T2
23
DS
R2
24
NC
DB0~DB7
CS1,CS2
RSLCT0,RSLCT1
W,R
TRNRDY1
RCVRDY1
RCVRDY1
SYNC,BRK1
TRNEMP1
RST
TRNRDY2
RCVRDY2
RCVRDY2
SYNC/BRK2
TRNEMP2
CLOCK
SDTR1
TRNDT1
RTS1
DTR1
RTS1
DTR1
RCVDT1
CTS1
DSR1
DSR1
TRNCLK1
RCVCLK1
SDTR2
TRNDT2
RTS2
RTS2
DTR2
RCVDT2
CTS2
DSR2
CTS2
DSR2
TRNCLK2
RCVCLK2
Address
decoder
Mode setting
register 1
Baud rate
setting
register 1
Baud rate
generator
Mode setting
register 2
Baud rate
setting
register 2
Interrup-
tion
mask 1
Loop
back
control
1
Loop
back
control
2
Interrup-
tion
mask 2
Clock
control
1
Clock
control
2
VCC
GND
3 – 5
4) Pin description
No.
Pin No.
Pin name
I/O
ER-A5RS
Data bus
1
1
DB4
I/O
DB4
2
2
DB5
I/O
DB5
3
3
DB6
I/O
DB6
4
4
DB7
I/O
DB7
5
41
DB0
I/O
DB0
6
42
DB1
I/O
DB1
7
44
DB2
I/O
DB2
8
45
DB3
I/O
DB3
9
46
RCVDT1
I
RCVDT1
RS-232 reception data signal
10
13
RCVDT2
I
RCVDT2
11
47
GND
–
GND
12
5
TRNCLK1-
I
GND
Data transmission clock
13
15
TRNCLK2-
I
GND
14
6
W-
I
W-
Write signal
15
7
CS1-
I
CS1-
RS-232 chip select
16
12
CS2-
I
CS2-
17
8
RSLCT0
I
AB0
Address bus
18
11
RSLCT1
I
AB1
19
9
R-
I
R-
Read signal
20
10
RCVRDY1
O
RCVRDY1
RS-232 data reception enable signal
21
16
RCVRDY2
O
RCVRDY2
22
28
TRNRDY1
O
TRNRDY1
RS-232 data transmission enable signal
23
17
TRNRDY2
O
TRNRDY2
24
29
BRK1
O
BRK1
Break code detection signal
25
18
BRK2
O
BRK2
26
30
CTS1-
I
(CTS1-)GND
RS-232 clear to send signal
27
20
CTS2-
I
(CTS2-)GND
28
31
TRNEMP1
O
TRNEMP1
RS-232 transmission buffer empty signal
29
21
TRNEMP2
O
TRNEMP2
30
14
NC
–
NC
31
24
NC
–
NC
32
38
NC
–
NC
33
48
NC
–
NC
34
19
OPEN
NC
35
43
OPEN
NC
36
32
TRNDT1
O
TRNDT1
RS-232 transmission data signal
37
22
TRNDT2
O
TRNDT2
38
35
DSR1-
I
DSR1-
RS-232 data set ready signal
39
23
DSR2-
I
DSR2-
40
36
RTS1-
O
NC
Request to send signal
41
25
RTS2-
O
NC
42
37
DTR1-
O
DTR1-
RS-232 data terminal ready signal
43
26
DTR2-
O
DTR1-
44
39
RCVCLK1-
I
GND
Data reception clock
45
27
RCVCLK2-
I
GND
46
33
CLOCK
I
CLOCK
Clock signal
47
34
RST
I
RES
RESET signal
48
40
VCC
–
+5V
+5V
3 – 6
4. Power supply circuit
The ER-A495G supplies +5V to +24V, and
±
12V is generated from
+24V in the DC/DC convertor circuit.
Fig. 4-1
(1)
The PX signal from the OPC1 alternately turns on and off the
comparator output of IC 8 (pin 7), which causes Q1 to turn on
and off. (Circuit
comparator output of IC 8 (pin 7), which causes Q1 to turn on
and off. (Circuit
A
)
Fig. 4-2
T1: Software starting:
26.04us
Normal operation:
13.02us
*
After POFF cancel (Power ON), software start is made for
13.3ms.
Duty (Q1: ON/OFF) : Software strating: 12.5%
Noemalperation : 25%
(2)
The potential at point
a
is 4.8V when the output voltage is
+12V(About +11V). A load fluctuation causes the +12V output to
change. At point
change. At point
b
of the comparators (+) side, a triangular
waveform appears as shown in Fig. 4-2.
(3)
The comparator (IC No. 8...Circuit
B
), the potential at point
a
is compared with that of point
b
. If the potential at point
a
is
lower than point
b
, Q1 activating time is prolonged to raise
the output voltage (by increasing the duty cycle). On the con-
trary, if the potential at point
trary, if the potential at point
a
is higher, the transistor activat-
ing time is hortened to decrease the output voltage (by decreas-
ing the duty cycle). As Q1 duties cycles are varied by detecting
the +12V output fluctuation in the comparator (Circuit
ing the duty cycle). As Q1 duties cycles are varied by detecting
the +12V output fluctuation in the comparator (Circuit
B
), the
output voltage is regulated at a constant level.
Fig. 4-3
Potential at point a changes according to a fluctuation in the
+12V output. Waveform at point a differs depending on the state
of +12V output.
+12V output. Waveform at point a differs depending on the state
of +12V output.
(4)
The pin 3 output of the IC9 chip at circuit
C
is at a high level
when the pin 1 input is at 5V. But, when it drops below 4.5V, the
line goes to the GND level. This causes Q1 to turn off so that
+12V and 12V are shut off. It is provided for prevention from
malfunction in the logic circuit when the +5V supply from mal-
function in the logic circuit when the +5V supply from the ER-
A495G main frame drops.
line goes to the GND level. This causes Q1 to turn off so that
+12V and 12V are shut off. It is provided for prevention from
malfunction in the logic circuit when the +5V supply from mal-
function in the logic circuit when the +5V supply from the ER-
A495G main frame drops.
*
IC9: Not used
5. ER-A5RS channel setting
The ER-A5RS ports can be set to channel 1 - 7 and invalid (inhibit)
with SW1 on the PWB.
with SW1 on the PWB.
SW1 setting contents
SW1 1~3 are used for channel setting of RS-232 connector 1
(RSCN1).
SW1 4~6 are used for channel setting of RS-232 connector 2
(RSCN2).
SW1 1~3 are used for channel setting of RS-232 connector 1
(RSCN1).
SW1 4~6 are used for channel setting of RS-232 connector 2
(RSCN2).
+24V
+24V
+5V
+12V
-12V
T800mA
+ C49
100µ
50V
R22
4.3K
IC 9
1
2
D 2
+
+
C 51
C 52
RD33EB1
ZD 2
R 17
2.7KG
8
4
2
3
+
-
R14
10KG
C28
330P
R13
100K G
+
-
6
5
R16
R15
10K
10K
C
B
A
Q1
ZD1
RD27EB4
T1
H6752RC
+5V
3
D 3
100µ35V x 2
R24
2.2K
1
R18
2.2KG
IC8
9393
7
IC8
9393
D1
E352
C50
10µ
16V
ZD3
RD5.1EL1
PX
c
a
b
+5V
GND
OFF
ON
+5V
GND
OFF
ON
OFF
PX
Q1
ON,OFF
ON,OFF
c
Point
3.255µs
T1
ON
OFF
ON
ON
OFF
OFF
OFF
+5V
GND
500mV
+4.8V
+1.4V
GND
GND
+1.4V
+4.8V
+5V
PX
Q1
ON, OFF
ON, OFF
Point
a
b
c
Point
Point
a
Point
c
Point
+3V
*1
*2
*3
(a)
(0)
(1)
SW1
RSCN1
RSCN2
OPTCN1
SW1
RSCN1
setting
3
2
1
0
0
0
RS-232 invalid
0
0
1
Channel 1
0
1
0
Channel 2
0
1
1
Channel 3
1
0
0
Channel 4
1
0
1
Channel 5
1
1
0
Channel 6
1
1
1
Channel 7
SW1
RSCN2
setting
6
5
4
0
0
0
RS-232 invalid
0
0
1
Channel 1
0
1
0
Channel 2
0
1
1
Channel 3
1
0
0
Channel 4
1
0
1
Channel 5
1
1
0
Channel 6
1
1
1
Channel 7
Note
1) If RSCN1 port and RSCN2 port of the ER-A5RS are set to the
1) If RSCN1 port and RSCN2 port of the ER-A5RS are set to the
same channel, RSCN2 port becomes invalid and only RSCN1 is
valid.
valid.
2) If RSCN of the ER-A5RS connector are set to the same channel,
the buses compete and the operation cannot be assured. In addi-
tion, it may break the hardware. Never set the two to the same
channel. Be sure to set them to different channels or to set invalid.
tion, it may break the hardware. Never set the two to the same
channel. Be sure to set them to different channels or to set invalid.
6
5
4
3
2
1
O
F
F
1
0
6
5
4
CN2
3
2
1
CN1
3 – 7
6. CI signal setting
On the ER-A5RS’s RS-232 connector 2 (RSCN2), the select jumper
switch of CI signal/+5V is added.
switch of CI signal/+5V is added.
Applicable version: N7292BH-58
Production month: From 1995/November production
Production month: From 1995/November production
JP1 position
Function: RSCN2 9-pin output
CI side
(Factory setting)
RS-232 CI signal output
Device connection requiring CI signal
Device connection requiring CI signal
+5V side
+5V voltage output
Device connection requiring +5V voltage.
Device connection requiring +5V voltage.
RSCN1
RSCN2
JP1
3 – 8
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