Sharp ER-A490 (serv.man2) Service Manual ▷ View online
8. Drawer drive circuit
Fig. 8-1
The drawer is directly supported by the CPU. No action starts when
the power supply is not steady as the output stage of the driver is
pulled VP by VRESC signal.
Drawer open and close is sensed with the microswitch provided in the
drawer whose signal is level converted with R74 and R73 and directly
read by the CPU.
the power supply is not steady as the output stage of the driver is
pulled VP by VRESC signal.
Drawer open and close is sensed with the microswitch provided in the
drawer whose signal is level converted with R74 and R73 and directly
read by the CPU.
9. Key, display, timer, buzzer controls
The keys, switches, displays, timer/calendar, and buzzer are control-
led by the CKDC-4 on the display PWB.
led by the CKDC-4 on the display PWB.
Block diagram
Fig. 9-1
DR0
DRAW0
52
50
DOSP
C52
1000P
R29
4.7K
4.7K
TD62308F
R30 22K
51
DR1
DRAW1
VRESC
CPU
+24V
Drawer
solenoid
solenoid
+24V
R28
47K
47K
IRQ
SHEN
STH
HTS
SCK
POFF
STOP
SRES
SHEN
STH
HTS
SCK
POFF
STOP
SRES
CKDCR
HOST
SYSTEM
SYSTEM
7SEG-DISPLAY 10DIG
DOT-DISPLAY 12DIG
G1~
G
1
0
SA~
SG
P0
,1
,4
CKDC 6
P2,3
DI
G
0
0
DI
G
1
1
PO
T
0
0
PO
T
3
5
DOT DISP CONT.
M66004FP
M66004FP
SRES,DCS,DSCK,DSO
ST0~3
KEX0,1
DECODER
LS138
LS138
DECODER
LS138
LS138
DECODER
HC153
HC153
DECODER
HC153
HC153
DI
S
PSL
SKR
O
Q
BUZZ
BUZZER
CSFR
MODR
MODR
KR
0
~
3
7SEG-DISPLAY 7DIG
Pop-up display
KEY BOARD
MAX. 128key
+ Paper feed key
(R and J)
+ Paper feed key
(R and J)
28
1) Power on/off sequence
Fig. 9-2
Hatched area indicates logic unstable.
<At power on>
When +24V power rises, the signal POFF is forced high (A), by which
time the +5V supply becomes stable. The CKDC6 monitors the state
of POFF while updating the timer/calendar in the low power standby
mode, and when the high state of POFF is detected, the system reset
signal (RESET) is set high (B), by which time the output lines STOP
and SCK of the CPU and MPCA6 have been initialized to high, re-
spectively (C). Thereafter, the CKDC6 sets SHEN active (low) (D) to
notify the CPU of the command/data communication ready state.
One byte data/command can be transferred with eight SCK pulses
(F). When one byte has been transferred with eight SCK pulses, the
CKDC6 sets SHEN high to initiate internal processing. After comple-
tion of the internal processing, when the next byte transfer becomes
ready, the CKDC6 sets SHEN back to a low state to wait for the next
byte transfer (G).
Thereafter, the SHEN and SCK timing described above is repeated to
carry on the communication.
time the +5V supply becomes stable. The CKDC6 monitors the state
of POFF while updating the timer/calendar in the low power standby
mode, and when the high state of POFF is detected, the system reset
signal (RESET) is set high (B), by which time the output lines STOP
and SCK of the CPU and MPCA6 have been initialized to high, re-
spectively (C). Thereafter, the CKDC6 sets SHEN active (low) (D) to
notify the CPU of the command/data communication ready state.
One byte data/command can be transferred with eight SCK pulses
(F). When one byte has been transferred with eight SCK pulses, the
CKDC6 sets SHEN high to initiate internal processing. After comple-
tion of the internal processing, when the next byte transfer becomes
ready, the CKDC6 sets SHEN back to a low state to wait for the next
byte transfer (G).
Thereafter, the SHEN and SCK timing described above is repeated to
carry on the communication.
<At power off>
When +24V power drops, POFF goes low (H).
A low on the POFF line causes a low level interrupt request which is
sent the IRQ0 pin of the CPU. Within a maximum of 10msec of the
low level IRQ0 input, the CPU performs software processing neces-
sary for power-off, after which the STOP output is set low (I).
When STOP goes low, the CKDC6 sets RESET low to reset the
whole system (J). And, the +5V supply is held at 4.75V or higher
voltage, after which the voltage drops to a level that the logic circuit
does not operate.
A low on the POFF line causes a low level interrupt request which is
sent the IRQ0 pin of the CPU. Within a maximum of 10msec of the
low level IRQ0 input, the CPU performs software processing neces-
sary for power-off, after which the STOP output is set low (I).
When STOP goes low, the CKDC6 sets RESET low to reset the
whole system (J). And, the +5V supply is held at 4.75V or higher
voltage, after which the voltage drops to a level that the logic circuit
does not operate.
2) Key and switch scanning
Strobes ST0 ~ ST3 are decoded on the keyboard by two 74LS138 3-
to-8 decoders to generate 16 strobe signals of S15 ~ S0.
The key matrix consists of 16 strobe lines and 16 returns lines of
KR0A, KR1A, KR2A, KR3A, KR0B, KR1B, KR2B, and KR3B.
To minimize interfacing lines between the CKDC6 and the keyboard
unit, two multiplexers (74HC153) are used to multiplex signals by the
timing controlled with the signals KEX0 and KEX1 which are sent to
the CKDC6 on the return lines of KR0 ~ KR3.
to-8 decoders to generate 16 strobe signals of S15 ~ S0.
The key matrix consists of 16 strobe lines and 16 returns lines of
KR0A, KR1A, KR2A, KR3A, KR0B, KR1B, KR2B, and KR3B.
To minimize interfacing lines between the CKDC6 and the keyboard
unit, two multiplexers (74HC153) are used to multiplex signals by the
timing controlled with the signals KEX0 and KEX1 which are sent to
the CKDC6 on the return lines of KR0 ~ KR3.
Timing ST
Fig. 9-3
The mode switch in provided with a special return line MODR, apart
from the above return lines.
In the same manner, the clerk, paper feed key (J/R), and receipt
on/off switches use CFSR as the return line.
from the above return lines.
In the same manner, the clerk, paper feed key (J/R), and receipt
on/off switches use CFSR as the return line.
3) DISPLAY CONTROL
Fig. 9-4
CKDC6 directly drives the 7-segment display unit and the dot display
is driven via M66004FP.
is driven via M66004FP.
<7-segment display>
Fig. 9-5
A
B
C
D
G
I
J
E
F
H
+5V
POFF
RESET
STOP
SHEN
SCK
+24V
12.45ms
778µ S
10µ S 10µ S 10µ S
KR0A
KR3A
KR0B
KR3B
80µ S
ST3
S15
ST2
ST1
ST0
S14
ST0
KEX0
KEX1
KR0~KR3
S//
RES
DSO
DSCK
DCS
+5V
DG0~
DG11
DG11
Display
controller
M66004
FP
DDIG
SO2
SCK2
SDISP
SA~SG
DP,ID
G1~10
7SEG-Display
D0~D35
DOT-Display
16
CKDC 6
976µS
15µS
44.8µS
58µS
Gm
SA,SB,SC,SD
SE,SF,SG
SE,SF,SG
DP,ID
Gm+1
976µS x n
29
<Dot display>
Fig. 9-6
IMPORTANT:
The CKDC6 lines are not high voltage resistive ports. Damage may
occur to the CKDC6 if lines are shorted carelessly when using oscillo-
scope probes.
occur to the CKDC6 if lines are shorted carelessly when using oscillo-
scope probes.
•
Dot matrix tube
A 4-bit binary output signals (ST0-ST3) from CDKC6 are converted
into the digit drive signal (DG0-DG11) in the M66004FP.
A 4-bit binary output signals (ST0-ST3) from CDKC6 are converted
into the digit drive signal (DG0-DG11) in the M66004FP.
<Dot display control>
The CKDC6 controls the character segment (5 x 7) and the indicator
of the dot display by using the controller (M66004FP) for dot display
control.
of the dot display by using the controller (M66004FP) for dot display
control.
1
M66004FP/Dot display control signal
Signal
name
Contents
Pin/Remark
DSO
Serial data output signal
for M66004FP
for M66004FP
C-MOS pin
DSCK
Serial shift clock output
signal for M66004FP
signal for M66004FP
C-MOS pin.
Requires to be pulled up
Requires to be pulled up
DCS
Chip select output signal
for M66004FP
for M66004FP
C-MOS pin
10. Power supply circuit
Fig. 10-1
+24V:
Printer, solenoid power
+5V:
VCC (Logic power)
VBAT:
Battery charge
–32V:
Display tube power
VF1, VF2:
Display tube power (AC)
VRAM:
Battery back-uped power
VCKDC:
CKDC-6 Back-up power
VCH:
Fiscal memory unit
11. Switching regulator circuit
ENST
ST0~ST3
19.1µ s
DGn
"h" th digit
display
DGn+1
Display off
D0~D35
"h" th didit display pattern
(h+1) th didit display pattern
17.2µ s
(h+1) th digit display
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
: Indicator
VBAT
Power
trans.
trans.
DC-DC
Converter
circuit
Battery
circuit
circuit
VRAM
+5V
-32V
VF1/VF2
VF1/VF2
F1
F2
Switching
regulator
(STR2124)
+24V
+
-
~
~
VCKDC
VCH
30
500KHz
"0"
"1"
"0"
"1"
16-division
3/16
UART
Reverse
UART
UART
IRDA
ASK
58.5~76.5 ms
108 ms
108 ms
9 ms
4.5 ms
13.5 ms
Leader Code
Custom Code
8 bits
8 bits
Custom Code'
8 bits
8 bits
Data Code
8 bits
8 bits
27 ms
18 ms~36 ms
58.5 ms~76.5 ms
Data Code
8 bits
8 bits
9 ms
4.5 ms
13.5 ms
1.125 ms
2.25 ms
0
1
1
0
0
1
9 ms
2.25 ms
11.25 ms
0.56 ms
Time is the value for 455kHz oscillation.
First
time
time
Carrier waveform
Carrier frequency.....fc=fosc/12=38 khz
Second time and later
(Transmitted only when the key is depressed.)
(Transmitted only when the key is depressed.)
8.77µs
26.3µs
9 ms or 0.56 ms
<Remote keyboard>
0.56 ms
System
IRDA
ASK
REMOTE KEYBOARD
Carrier wave
950 nm
900
∼
1050 nm
900
∼
950 nm
Sub-carrier wave
(16 times of baud rate clock)
500 kHz
±
10%
33
∼
40 kHz
Modulation
system
system
"0": HIGH level
"1": LOW level
Only around the center of the bit cycle
in HIGH level, 3/16 of the bit cycle is set
HIGH, and the rest is set LOW.
"1": LOW level
Only around the center of the bit cycle
in HIGH level, 3/16 of the bit cycle is set
HIGH, and the rest is set LOW.
Pulse modulation:
The pulse array of data code is
modulated by the AM system.
The pulse array of data code is
modulated by the AM system.
Pulse modulation:
The pulse array is modulated by data
codes in the PPM system.
The pulse array is modulated by data
codes in the PPM system.
Primary modulation:
The sub-carrier waveform is
amplitude-modulated with this pulse
array.
The sub-carrier waveform is
amplitude-modulated with this pulse
array.
Primary modulation:
The sub-carrier waveform is
amplitude-modulated with this pulse
array.
The sub-carrier waveform is
amplitude-modulated with this pulse
array.
Secondary modulation:
With the sub-carrier waveform which
was modulated in the primary
modulation, infra-red rays are
amplitude-modulated.
With the sub-carrier waveform which
was modulated in the primary
modulation, infra-red rays are
amplitude-modulated.
Secondary modulation:
With the sub-carrier waveform which
was modulated in the primary
modulation, infra-red rays are
amplitude-modulated.
With the sub-carrier waveform which
was modulated in the primary
modulation, infra-red rays are
amplitude-modulated.
Modulated
waveform
waveform
Baud rate
2.4
∼
115.2 kbps
9.6
∼
57.6 kbps (ZR-5000: 9600 bps)
—
Serial
communication
system
communication
system
Start-stop synchronization system
Data length: 8bit
Parity:
Data length: 8bit
Parity:
None
Stop bit:
1
Start-stop synchronization system
Data length: 8bit
Parity:
Data length: 8bit
Parity:
ODD
Stop bit:
1
—
Transmission
distance
distance
About 0.75m: ECR to ECR
Min. 0.65m
Min. 0.65m
About 0.75m: ECR to ECR
Min. 0.65m
Min. 0.65m
About 1m
31
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