Sharp SD-PX15H (serv.man20) Service Manual ▷ View online
SD-PX15H
8 – 13
IC3401 RH-iX0614AWZZ: 64M S-DRAM (IX0614AW) (2/2)
Pin No.
Terminal Name
Input/Output
Function
81
VDDQ
Input
Power supply for the output buffer.
82, 83
DQ13, DQ14
Input/Output
Multi data input/output pin.
84
VSSQ
—
GND.
85
DQ15
Input/Output
Multi data input/output pin.
86
VSS
—
GND.
86pin TSOP ll
400mll x 875mll
0.5mm pin pitch
V
DD
DQ0
V
DDQ
DQ1
DQ2
DQ2
V
SSQ
DQ3
DQ4
DQ4
V
DDQ
DQ5
DQ6
DQ6
V
SSQ
DQ7
NC
V
DD
DQM0
/WE
/CAS
/RAS
/RAS
/CS
NC
BA0
BA1
BA1
A10/AP
A0
A1
A2
A1
A2
DQM2
V
DD
NC
DQ16
V
SSQ
DQ17
DQ18
DQ18
V
DDQ
DQ19
DQ20
DQ20
V
SSQ
DQ21
DQ22
DQ22
V
DDQ
DQ23
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
V
SS
DQ15
V
V
SSQ
DQ14
DQ13
V
DQ13
V
DDQ
DQ12
DQ11
V
DQ11
V
SSQ
DQ10
DQ9
V
DQ9
V
DDQ
DQ8
NC
V
NC
V
SS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
SS
NC
DQ31
V
DQ31
V
DDQ
DQ30
DQ29
V
DQ29
V
SSQ
DQ28
DQ27
V
DQ27
V
DDQ
DQ26
DQ25
V
DQ25
V
SSQ
DQ24
V
V
SS
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
Figure 8-13 BLOCK DIAGRAM OF IC
SD-PX15H
8 – 14
IC3501 RH-iX3590CEZZ: Flash ROM (IX3590CE) (1/2)
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Pin No.
Terminal Name
Input/Output
Function
1-9
A15-A8, A19
Input
Memory address input: Address input for writing and reading. Addresses are latched internally dur-
ing a write cycle.
A1: least significant address input in byte mode (BYTE# = VIL),
data input/output DQ15 in the word mode (BYTE# = VIH)
A15- A19: main block selection address
A12- A19: boot/parameter block selection address
ing a write cycle.
A1: least significant address input in byte mode (BYTE# = VIL),
data input/output DQ15 in the word mode (BYTE# = VIH)
A15- A19: main block selection address
A12- A19: boot/parameter block selection address
10
N.C.
—
No connection: Not connected internally. (can also be connected)
11
WE#
Input
Write enable: Writing to the CUI and array block is controlled. Activated when WE# = VIL. Addresses
and data are latched on the rising edge of WE# pulse.
and data are latched on the rising edge of WE# pulse.
12
RP#
Input
Reset: It is activated and automatically reset internally when RP# = VIL. The device operates nor-
mally when RP# = VIH. When RP# = VIL, writing is prohibited and data is protected. After recovering
from the reset mode, the device enters the array readout status. Make sure to set VIL when turning
on the power.
mally when RP# = VIH. When RP# = VIL, writing is prohibited and data is protected. After recovering
from the reset mode, the device enters the array readout status. Make sure to set VIL when turning
on the power.
13
VCCW
Input
Block erase, full chip erase, word/byte write and lock bit configuration power supply: Memory data is
not changed when VCCW VCCWLK. Operations with improper voltage may cause malfunction or
breakage. When VCCW voltage is 12 ± 0.3 V, data can be rewritten up to 1,000 times per block.
When applying 12 ± 0.3 V to VCCW pin, total application time must be no longer than 80 hours.
not changed when VCCW VCCWLK. Operations with improper voltage may cause malfunction or
breakage. When VCCW voltage is 12 ± 0.3 V, data can be rewritten up to 1,000 times per block.
When applying 12 ± 0.3 V to VCCW pin, total application time must be no longer than 80 hours.
14
WP#
Input
Write protect: When WP# = VIL, the boot block is protected from writing and erasing. Even when
WP# = VIH, writing and erasing are prohibited if the block lock bit is set. For the parameter/main
block, writing and erasing are controlled by the block lock bit status regardless of WP#.
WP# = VIH, writing and erasing are prohibited if the block lock bit is set. For the parameter/main
block, writing and erasing are controlled by the block lock bit status regardless of WP#.
15*
RY/BY#
Output
Ready/Busy: The status of the internal Write State Machine (WSM) is sent. When VIL is supplied,
WSM is working (block erase, full chip erase, word/byte write, and lock bit configuration). When RY/
BY# = HighZ, WSM is waiting for the next command; word/byte write is not executed with block
erase suspended; word/byte write is suspended; or WSM is in the reset mode.
WSM is working (block erase, full chip erase, word/byte write, and lock bit configuration). When RY/
BY# = HighZ, WSM is waiting for the next command; word/byte write is not executed with block
erase suspended; word/byte write is suspended; or WSM is in the reset mode.
16, 17
A18, A17
Input
Memory address input: Address input for writing and reading. Addresses are latched internally dur-
ing a write cycle.
A1: least significant address input in byte mode (BYTE# = VIL),
data input/output DQ15 in the word mode (BYTE# = VIH)
A15- A19: main block selection address
A12- A19: boot/parameter block selection address
ing a write cycle.
A1: least significant address input in byte mode (BYTE# = VIL),
data input/output DQ15 in the word mode (BYTE# = VIH)
A15- A19: main block selection address
A12- A19: boot/parameter block selection address
19-25
A7-A0
Input
Memory address input: Address input for writing and reading. Addresses are latched internally dur-
ing a write cycle.
A1: least significant address input in byte mode (BYTE# = VIL),
data input/output DQ15 in the word mode (BYTE# = VIH)
A15- A19: main block selection address
A12- A19: boot/parameter block selection address
ing a write cycle.
A1: least significant address input in byte mode (BYTE# = VIL),
data input/output DQ15 in the word mode (BYTE# = VIH)
A15- A19: main block selection address
A12- A19: boot/parameter block selection address
26
CE#
Input
Chip enable: Control logic, input buffer decoder, sense amplifier of the device are activated when
CE# = VIL. When CE# = VIH, the device is not selected and power consumption is reduced to the
stand-by level.
CE# = VIL. When CE# = VIH, the device is not selected and power consumption is reduced to the
stand-by level.
27
GND
—
Ground: Connect all the ground pins.
28
OE#
Input
Output enable: Device output is controlled during a read cycle. Activated when OE# = VIL.
29, 30
DQ0, DQ8
Input/Output
Data input/output: Data/command input, memory array, and status register during a Command User
Interface (CUI) write cycle. Data output during an ID code read cycle. When a chip is not selected or
output is disabled, the pin goes to the floating state. Data is latched internally in a write cycle. In the
byte mode, DQ8 - DQ15 are not used and DQ15 becomes address input (A-1).
Interface (CUI) write cycle. Data output during an ID code read cycle. When a chip is not selected or
output is disabled, the pin goes to the floating state. Data is latched internally in a write cycle. In the
byte mode, DQ8 - DQ15 are not used and DQ15 becomes address input (A-1).
31, 32
DQ1, DQ9
Input/Output
Data input/output: Data/command input, memory array, and status register during a Command User
Interface (CUI) write cycle. Data output during an ID code read cycle. When a chip is not selected or
output is disabled, the pin goes to the floating state. Data is latched internally in a write cycle. In the
byte mode, DQ8 - DQ15 are not used and DQ15 becomes address input (A-1).
Interface (CUI) write cycle. Data output during an ID code read cycle. When a chip is not selected or
output is disabled, the pin goes to the floating state. Data is latched internally in a write cycle. In the
byte mode, DQ8 - DQ15 are not used and DQ15 becomes address input (A-1).
33, 34
DQ2, DQ10
Input/Output
Data input/output: Data/command input, memory array, and status register during a Command User
Interface (CUI) write cycle. Data output during an ID code read cycle. When a chip is not selected or
output is disabled, the pin goes to the floating state. Data is latched internally in a write cycle. In the
byte mode, DQ8 - DQ15 are not used and DQ15 becomes address input (A-1).
Interface (CUI) write cycle. Data output during an ID code read cycle. When a chip is not selected or
output is disabled, the pin goes to the floating state. Data is latched internally in a write cycle. In the
byte mode, DQ8 - DQ15 are not used and DQ15 becomes address input (A-1).
35, 36
DQ3, DQ11
Input/Output
Data input/output: Data/command input, memory array, and status register during a Command User
Interface (CUI) write cycle. Data output during an ID code read cycle. When a chip is not selected or
output is disabled, the pin goes to the floating state. Data is latched internally in a write cycle. In the
byte mode, DQ8 - DQ15 are not used and DQ15 becomes address input (A-1).
Interface (CUI) write cycle. Data output during an ID code read cycle. When a chip is not selected or
output is disabled, the pin goes to the floating state. Data is latched internally in a write cycle. In the
byte mode, DQ8 - DQ15 are not used and DQ15 becomes address input (A-1).
37
VCC
Input
Device power supply: When VCC? VLKO, the flash memory is protected from writing. Improper VCC
voltage may cause malfunction.
voltage may cause malfunction.
38, 39
DQ4, DQ12
Input/Output
Data input/output: Data/command input, memory array, and status register during a Command User
Interface (CUI) write cycle. Data output during an ID code read cycle. When a chip is not selected or
output is disabled, the pin goes to the floating state. Data is latched internally in a write cycle. In the
byte mode, DQ8 - DQ15 are not used and DQ15 becomes address input (A-1).
Interface (CUI) write cycle. Data output during an ID code read cycle. When a chip is not selected or
output is disabled, the pin goes to the floating state. Data is latched internally in a write cycle. In the
byte mode, DQ8 - DQ15 are not used and DQ15 becomes address input (A-1).
SD-PX15H
8 – 15
IC3501 RH-iX3590CEZZ: Flash ROM (IX3590CE) (2/2)
Pin No.
Terminal Name
Input/Output
Function
40, 41
DQ5, DQ13
Input/Output
Data input/output: Data/command input, memory array, and status register during a Command User
Interface (CUI) write cycle. Data output during an ID code read cycle. When a chip is not selected or
output is disabled, the pin goes to the floating state. Data is latched internally in a write cycle. In the
byte mode, DQ8 - DQ15 are not used and DQ15 becomes address input (A-1).
Interface (CUI) write cycle. Data output during an ID code read cycle. When a chip is not selected or
output is disabled, the pin goes to the floating state. Data is latched internally in a write cycle. In the
byte mode, DQ8 - DQ15 are not used and DQ15 becomes address input (A-1).
42, 43
DQ6, DQ14
Input/Output
Data input/output: Data/command input, memory array, and status register during a Command User
Interface (CUI) write cycle. Data output during an ID code read cycle. When a chip is not selected or
output is disabled, the pin goes to the floating state. Data is latched internally in a write cycle. In the
byte mode, DQ8 - DQ15 are not used and DQ15 becomes address input (A-1).
Interface (CUI) write cycle. Data output during an ID code read cycle. When a chip is not selected or
output is disabled, the pin goes to the floating state. Data is latched internally in a write cycle. In the
byte mode, DQ8 - DQ15 are not used and DQ15 becomes address input (A-1).
44, 45
DQ7, DQ15
Input/Output
Data input/output: Data/command input, memory array, and status register during a Command User
Interface (CUI) write cycle. Data output during an ID code read cycle. When a chip is not selected or
output is disabled, the pin goes to the floating state. Data is latched internally in a write cycle. In the
byte mode, DQ8 - DQ15 are not used and DQ15 becomes address input (A-1).
Interface (CUI) write cycle. Data output during an ID code read cycle. When a chip is not selected or
output is disabled, the pin goes to the floating state. Data is latched internally in a write cycle. In the
byte mode, DQ8 - DQ15 are not used and DQ15 becomes address input (A-1).
46
GND
—
Ground: Connect all the ground pins.
47
BYTE#
Input
Byte enable: When BYTE# = VIL, the device enters the byte mode (x8). At this time, DQ8 - 14 pins
go into HighZ state and DQ15/A-1 becomes least significant address input (A-1). When BYTE# =
VIH, the device goes into the word mode (x16) and DQ15/A-1 pin becomes data input/output DQ15.
go into HighZ state and DQ15/A-1 becomes least significant address input (A-1). When BYTE# =
VIH, the device goes into the word mode (x16) and DQ15/A-1 pin becomes data input/output DQ15.
48
A16
Input
Memory address input: Address input for reading and writing. Addresses are latched internally dur-
ing a write cycle.
A1: least significant address input in byte mode (BYTE# = VIL),
data input/output DQ15 in the word mode (BYTE# = VIH)
A15- A19: main block selection address
A12- A19: boot/parameter block selection address
ing a write cycle.
A1: least significant address input in byte mode (BYTE# = VIL),
data input/output DQ15 in the word mode (BYTE# = VIH)
A15- A19: main block selection address
A12- A19: boot/parameter block selection address
48-LEAD TSOP
A15
A14
A13
A12
A11
A10
A14
A13
A12
A11
A10
A9
A8
A8
A19
NC
WE#
RP#
VCCW
WP#
RY/BY#
A18
A17
A17
A7
A6
A5
A4
A3
A2
A1
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
BYTE#
GND
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
GND
CE#
A0
BYTE#
GND
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
GND
CE#
A0
STANDARD PINOUT
TOP VIEW
12mm x 20mm
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Figure 8-15 BLOCK DIAGRAM OF IC
SD-PX15H
8 – 16
IC3704 VHiAN8785SB-1: Focus/Tracking/Spin/Sled Driver (AN8785SB)
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Pin No.
Terminal Name
Input/Output
Function
1
FCSN
Output
Driver 1 inversion output terminal.
2
TRK_IN
Input
Driver 5 input terminal.
3*
OP_OUT
Output
OP amplifier output terminal.
4*
OP_N
Input
OP amplifier inversion input terminal.
5*
OP_P
Input
OP normal rotation input terminal.
6
VREF
Input
VREF input terminal.
7
2.5V_OUT
Input/Output
Driver 2 normal rotation input terminal (2.5 V output terminal).
8
REFSEL
Input
Driver 4 normal rotation input switch terminal.
9*
LOAD_IN
Input
Driver 2 input terminal.
10
PVCC2
Input
Driver power supply terminal 2.
11*
LOADP
Output
Driver 2 normal rotation output terminal.
12*
LOADN
Output
Driver 2 inversion output terminal.
13
SPINP
Output
Driver 3 normal rotation output terminal.
14
SPINN
Output
Driver 3 inversion output terminal.
15
PGND2
—
Driver ground terminal 2.
16
NMUTE
Input
Stand-by input terminal.
17
SLDP
Output
Driver 4 normal rotation output terminal.
18
SLDN
Output
Driver 4 inversion output terminal.
19
PVCC3
Input
Driver power supply terminal 3.
20
SPIN_IN
Input
Driver 3 input terminal.
21
SLD_IN
Input
Driver 4 input terminal.
22
SVCC
Input
Power supply terminal.
23
FCS_IN
Input
Driver 1 input terminal.
24
PVCC1
Input
Driver power supply terminal 1.
25
TRKP
Output
Driver 5 normal rotation output terminal.
26
TRKN
Output
Driver 5 inversion output terminal.
27
PGND
—
Driver ground terminal 1.
28
FCSP
Output
Driver 1 normal rotation output terminal.
16
10
12
11
18
17
14
13
19
1
28
26
25
24
7
9
8
21
15
20
23
27
2
22
6
3
5
4
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
Standby
Standby
D2-
D2+
D4-
D4+
D3-
D3+
D1-
D1+
D5-
IN-
IN+
OUT
IN5
PGnd1
IN1
IN3
switch
1.25V
PGnd2
IN4
Ch.4 SW
IN2-
IN2+
SGnd-Fin
SV
CC
V
REF
D5+
Protection
Circuit
Circuit
Band-gap
V
CC
/V
REF
Reset Circuit
PV
CC3
PV
CC1
PV
CC2
Figure 8-16 BLOCK DIAGRAM OF IC
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