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Model
SD-PX15H (serv.man20)
Pages
98
Size
6.61 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio / System
File
sd-px15h-sm20.pdf
Date

Sharp SD-PX15H (serv.man20) Service Manual ▷ View online

SD-PX15H
8 – 9
IC3001 RH-iX0613AWZZ: DVD Decoder LSI (IX0613AW) (3/5)
Pin No.
Terminal Name
Input/Output
Function
120
RFINN
Input
RF input -.
121
RFINP
Input
RF input +.
122
VIN5
Input
CD head input.
123
VIN6
Input
CD head input.
124
VIN7
Input
DVD head input.
125
VIN8
Input
DVD head input.
126
VIN1
Input
DVD head input.
127
VIN2
Input
DVD head input.
128
VIN3
Input
DVD head input.
129
VIN4
Input
DVD head input.
130
VIN9
Input
CD head input.
131
VIN10
Input
CD head input.
132
LPC1
Input
DVD LPC input.
133
LPCO1
Output
DVD LPC output.
134
LPC2
Input
CD LPC input.
135
LPCO2
Output
CD LPC output.
136
VREFH
Output
Reference voltage 2.20 [V] output.
137
VHALF
Output
Reference voltage 1.65 [V] output.
138
AVSSB
Analog GND.
139
CTKC
Output
TEO capacitance connection.
140
CSLFLT
Input
CPDET capacitance connection.
141
CWBLOUT
Input
DC cut capacitance connection for wobble.
142
CWBLIN
Input
DC cut capacitance connection for wobble.
143
VCOF
Input
JFVCO control voltage.
144
RV1
Input
Resistance connection for VREFH reference current.
145
AVDDB
Input
Analog power supply.
146
AD2
Input
General purpose AD input. 
147
AD1
Input
General purpose AD input/Internal analog monitor.
148
AD0
Input
General purpose AD input. 
149
AVDDA
Input
Analog power supply.
150
DAC1
Output
Tracking drive output.
151
AVSSA
Analog GND.
152
DAC0
Output
Focus drive output.
153
AVDDE
Input
Analog power supply.
154
IREF1
Input
Resistance for setting internal DAC bias current.
155
AVSSE
Analog GND.
156
COMP1
Input
Internal DAC stabilization capacitance.
157
AVDDF
Input
Analog power supply.
158
DAC1OUT
Output
Y (brightness)/G (green) analog signals.
159
AVSSF
Analog GND.
160
DAC2OUT
Output
Cb (color difference)/B (blue) analog signals.
161
DAC3OUT
Output
Cr (color difference)/R (red) analog signals.
162
VREF
Input
Internal DAC reference voltage.
163
DAC4OUT
Output
Y (brightness)/Comp (composite) analog signals.
164
DAC5OUT
Output
C (color) analog signal.
165
AVDDG
Input
Analog power supply.
166
IREF2
Output
Resistance for setting internal DAC bias current.
167
AVSSG
Analog GND.
168
COMP2
Input
Internal DAC stabilization capacitance.
169
VSS
GND.
170
BECLK
Input
Back-end section clock input.
171
VDD33
Input
IO power supply.
172
EXTCK
Input
External audio clock/Stream clock output.
173
PHCOMPO
Output
Audio clock phase difference/Stream data output 7.
174
LRCK
Output
LR channel clock/Stream data output 6.
175
SRCK
Output
Bit clock/Stream data output 5
176
ADOUT3
Output
Audio down mix/Stream data output 4.
177
VSS
GND.
178
ADOUT2
Output
Audio data/Internal monitor 11/Stream data output 3.
179
ADOUT1
Output
Audio data/Internal monitor 10/Stream data output 2.
180
ADOUT0
Output
Audio data/Internal monitor 9/Stream data output 1.
181
IECOUT
Output
IEC958 digital audio out/Internal monitor 8/Stream data output 0.
182
VDD33
Input
IO power supply.
SD-PX15H
8 – 10
IC3001 RH-iX0613AWZZ: DVD Decoder LSI (IX0613AW) (4/5)
Pin No.
Terminal Name
Input/Output
Function
183
VSS
GND.
184
MDQ24
Input/Output
SDRAM data 24.
185
MDQ23
Input/Output
SDRAM data 23.
186
VDD15
Input
Internal logic power supply.
187
MDQ22
Input/Output
SDRAM data 22.
188
MDQ25
Input/Output
SDRAM data 25.
189
VDD33
Input
IO power supply.
190
MDQ26
Input/Output
SDRAM data 26.
191
MDQ21
Input/Output
SDRAM data 21.
192
MDQ27
Input/Output
SDRAM data 27.
193
MDQ20
Input/Output
SDRAM data 20.
194
VSS
GND.
195
VDD33
Input
IO power supply.
196
MDQ28
Input/Output
SDRAM data 28.
197
MDQ19
Input/Output
SDRAM data 19.
198
VSS
GND.
199
MDQ29
Input/Output
SDRAM data 29.
200
MDQ18
Input/Output
SDRAM data 18.
201
MDQ30
Input/Output
SDRAM data 30.
202
VDD33
Input
IO power supply.
203
MDQ17
Input/Output
SDRAM data 17.
204
MDQ31
Input/Output
SDRAM data 31.
205
MDQ16
Input/Output
SDRAM data 16.
206
VSS
GND.
207
DQM3
Output
SDRAM data mask 3.
208
DQM2
Output
SDRAM data mask 2.
209
VDD33
Input
IO power supply.
210
MA3
Output
SDRAM address 3.
211
VSS
GND.
212
MA4
Output
SDRAM address 4. 
213
VDD15
Input
Internal logic power supply.
214
MA2
Output
SDRAM address 2.
215
VSS
GND.
216
MA5
Output
SDRAM address 5.
217
MA1
Output
SDRAM address 1.
218
VDD33
Input
IO power supply.
219
MA6
Output
SDRAM address 6.
220
MA0
Output
SDRAM address 0.
221
VSS
GND.
222
VDD15
Input
Internal logic power supply.
223
MCKI
Input
SDRAM output clock.
224
VSS
GND.
225
MCK
Output
SDRAM input clock.
226
VDD33
Input
IO power supply.
227
MA7
Output
SDRAM address 7.
228
MA10
Output
SDRAM address 10.
229
MA8
Output
SDRAM address 8.
230
VSS
GND.
231
MA11
Output
SDRAM address 11.
232
NWE
Output
SDRAM write enable.
233
VDD33
Input
IO power supply.
234
BA0
Output
SDRAM bank address 0.
235
MA9
Output
SDRAM address 9.
236
VSS
GND.
237
BA1
Output
SDRAM bank address 1.
238
NCSM
Output
SDRAM chip selection.
239
NRAS
Output
SDRAM row address strobe.
240
VDD33
Input
IO power supply.
241
VSS
GND.
242
NCAS
Output
SDRAM column address strobe.
243
DQM0
Output
SDRAM data mask 0.
244
VDD15
Input
Internal logic power supply.
245
VSS
GND.
SD-PX15H
8 – 11
IC3001 RH-iX0613AWZZ: DVD Decoder LSI (IX0613AW) (5/5)
Pin No.
Terminal Name
Input/Output
Function
246
DQM1
Output
SDRAM data mask 1.
247
MDQ7
Input/Output
SDRAM data 7.
248
VSS
GND.
249
MDQ8
Input/Output
SDRAM data 8.
250
VDD33
Input
IO power supply.
251
MDQ6
Input/Output
SDRAM data 6.
252
MDQ9
Input/Output
SDRAM data 9.
253
MDQ5
Input/Output
SDRAM data 5.
254
VSS
GND.
255
MDQ10
Input/Output
SDRAM data 10.
256
MDQ4
Input/Output
SDRAM data 4.
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
27
28
29
26
192
191
190
189
188
187
186
185
184
183
182
181
180
179
80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79
MN2DS0002(iROM)
VDD33
MDQ11
MDQ3
VSS
MDQ12
MDQ2
VDD33
MDQ13
MDQ1
MDQ14
VSS
MDQ0
MDQ15
VDD33
VDD15
VSS
EXADR20
NEXWE
EXADT0
EXADT4
EXADT8
EXADT12
VDD33
VSS
EXADR16
EXADR18
EXADT14
EXADT10
VDD33
VSS
EXADT6
EXADT2
NEXCE
EXADT1
EXADT5
EXADT9
EXADT13
EXADR17
EXADR19
EXADT15
EXADT11
VDD33
VSS
EXADT7
EXADT3
NEXOE
P15
P14
P13
P12
P11
P10
P9
P8
P7
VDD3
MMOD
VSS
P6
P5
P4
P3
P2
P1
P0 FG
VDD15 NRST
VSS
DRV0 DRV1 DRV2 DRV3 DRV4 DRV5 DRV6 DRV7 DRV8 VDD33
VSS
SCLOCK EXTRG0
SDATA
EXTRG1 TRCCLK
TRCDATA0 TRCDATA1 TRCDATA2 TRCDATA3
TRCST VDD33
OSCI VSS
MONI7 MONI6 MONI5 MONI4 VDD15
VSS
MONI3 MONI2 MONI1 MONI0 AVDDD PLFIL1 AVSSD PLFIL2 VREFA VREFB VREFC
VC0 RESI
ANAMONI
POFLT CDATA CCAPA
CGD
AVDDC AVSSC RFINN RFINP
VIN5 VIN6 VIN7 VIN8 VIN1 VIN2 VIN3
241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193
256
255 254 253 252 251 250 249 248 247 246 245 244 243 242
MDQ27
MDQ21
MDQ26
VDD33
MDQ25
MDQ22
VDD15
MDQ23
MDQ24
VSS
VDD33
IECOUT
ADOUT0
ADOUT1
ADOUT2
VSS
ADOUT3
SRCK
LRCK
PHCOMPO
EXTCK
VDD33
BECLK
VSS
COMP2
AVSSG
IREF2
AVDDG
DAC5OUT
DAC4OUT
VREF
DAC3OUT
DAC2OUT
AVSSF
DAC1OUT
AVDDF
COMP1
AVSSE
IREF1
AVDDE
DAC0
AVSSA
DAC1
AVDDA
AD0
AD1
AD2
AVDDB
RVI
VCOF
CWBLIN
CWBLOUT
CSLFLT
CTKC
AVSSB
VHALF
VREFH
LPCO2
LPC2
LPCO1
LPC1
VIN10
VIN9
VIN4
MDQ4 MDQ10 VSS MDQ5 MDQ9 MDQ6 VDD33 MDQ8 VSS MDQ7 DQM1 VSS VDD15 DQM0 NCAS VSS VDD33 NRAS NCSM BA1 VSS MA9 BA0 VDD33 NWE MA11 VSS MA8 MA10 MA7 VDD33 MCK VSS MCKI VDD15 VSS MA0 MA6 VDD33 MA1 MA5 VSS MA2 VDD15 MA4 VSS MA3 VDD33 DQM2 DQM3 VSS MDQ16 MDQ31 MDQ17 VDD33 MDQ30 MDQ18 MDQ29 VSS MDQ19 MDQ28 VDD33 VSS MDQ20
LQFP256-P-2828
TOPVIEW
Figure 8-11 BLOCK DIAGRAM OF IC
SD-PX15H
8 – 12
IC3401 RH-iX0614AWZZ: 64M S-DRAM (IX0614AW) (1/2)
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Pin No.
Terminal Name
Input/Output
Function
1
VDD
Input
Power supply for internal circuits and the input buffer.
2
DQ0
Input/Output
Multi data input/output pin.
3
VDDQ
Input
Power supply for the output buffer.
4, 5
DQ1, DQ2
Input/Output
Multi data input/output pin.
6
VSSQ
GND.
7, 8
DQ3, DQ4
Input/Output
Multi data input/output pin.
9
VDDQ
Input
Power supply for the output buffer.
10, 11
DQ5, DQ6
Input/Output
Multi data input/output pin.
12
VSSQ
GND.
13
DQ7
Input/Output
Multi data input/output pin.
14*
N.C.
Not used.
15
VDD
Input
Power supply for internal circuits and the input buffer.
16
DQM0
Input/Output
Controls output buffer during read mode and masks input data during write mode.
17
WE
RAS, CAS and WE define operations.
18
CAS
RAS, CAS and WE define operations.
19
RAS
RAS, CAS and WE define operations.
20
CS
Input
All inputs except for CLK, CKE and DQM are enabled or disabled.
21
N.C.
Not used.
22, 23
BA0, BA1
The bank to be operated during RAS operation is selected.
The bank to read and write during CAS operation is selected.
24-27
A0-A2
Line address: RA0-RA10; Column address: CA0-CA7
Auto precharge flag: A10
28
DQM2
Input/Output
Controls output buffer during read mode and masks input data during write mode.
29
VDD
Input
Power supply for internal circuits and the input buffer.
30*
N.C.
Not used.
31
DQ16
Input/Output
Multi data input/output pin.
32
VSSQ
GND.
33, 34
DQ17, DQ18
Input/Output
Multi data input/output pin.
35
VDDQ
Input
Power source for the output buffer.
36, 37
DQ19, DQ20
Input/Output
Multi data input/output pin.
38
VSSQ
GND.
39, 40
DQ21, DQ22
Input/Output
Multi data input/output pin.
41
VDDQ
Input
Power source for the output buffer.
42
DQ23
Input/Output
Multi data input/output pin.
43
VDD
Input
Power supply for internal circuits and the input buffer.
44
VSS
GND.
45
DQ24
Input/Output
Multi data input/output pin.
46
VSSQ
GND.
47, 48
DQ25, DQ26
Input/Output
Multi data input/output pin.
49
VDDQ
Input
Power source for the output buffer.
50, 51
DQ27, DQ28
Input/Output
Multi data input/output pin.
52
VSSQ
GND.
53, 54
DQ29, DQ30
Input/Output
Multi data input/output pin.
55
VDDQ
Input
Power source for the output buffer.
56
DQ31
Input/Output
Multi data input/output pin.
57*
N.C.
Not used.
58
VSS
GND.
59
DQM3
Input/Output
Controls output buffer during read mode and masks input data during write mode.
60-66
A3-A9
Line address: RA0-RA10; Column address: CA0-CA7
Auto precharge flag: A10
67
CKE
Input
Controls internal clock signal. When the terminal is not operated, SDRAM is in either mode of 
Power Down, Suspend, or Self-refresh.
68
CLK
Input
System clock input. All other input is registered in SDRAM of CLK rise.
69*, 70* N.C.
Not used.
71
DQM1
Input/Output
Controls the output buffer during read mode and masks input data during write mode.
72
VSS
GND.
73*
N.C.
Not used.
74
DQ8
Input/Output
Multi data input/output pin.
75
VDDQ
Input
Power source for the output buffer.
76, 77
DQ9, DQ10
Input/Output
Multi data input/output pin.
78
VSSQ
GND.
79, 80
DQ11, DQ12
Input/Output
Multi data input/output pin.
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