Sharp HT-CN500DVH (serv.man3) Service Manual ▷ View online
– 39 –
HT-CN400DVH/HT-CN400DVE/HT-CN500DVH/HT-CN500DVE
FUNCTION TABLE OF IC
IC801 92LRCI6560-001: Motor Driver (LA6560)
1
FWD
Output change pin (FWD) for 5CH (VLO), logic input for loading block.
2
REV
Output change pin (REV) for 5CH (VLO), logic input for loading block.
3
VCC2
Power supply for CH3, 4 and 5.
4
VLO-
Loading output (-).
5
VLO+
Loading output (+).
6
VO4+
Output pin (+) for channel 4.
7
VO4-
Output pin (-) for channel 4.
8
VO3+
Output pin (+) for channel 3.
9
VO3-
Output pin (-) for channel 3.
10
VO2+
Output pin (+) for channel 2.
11
VO2-
Output pin (-) for channel 2.
12
VO1+
Output pin (+) for channel 1.
13
VO1-
Output pin (-) for channel 1.
14
VCC1
Power supply for CH1, 2 (BTL).
15
VIN1
Input pin for channel 1.
16
VIN1-A
OP-AMP input AMP-A input pin (-).
17
VIN1+A
OP-AMP input AMP-A input pin (+).
18
VIN1-B
Input AMP-B input pin (-) for channel 1.
19
VIN1+B
Input AMP-B input pin (+)for channel 1.
20
VIN2
Input pin for channel 2, input AMP output.
21
VIN2-
Input pin (-) for channel 2.
22
VIN2+
Input pin (+) for channel 2.
23
VIN3
Input pin for channel 3, input AMP output.
24
VIN3-
Input pin (-) for channel 3.
25
VIN3+
Input pin (+) for channel 3.
26*
REG-IN
PNP transistor base connected.
27*
REG-OUT
5 V power output to which the PNP transistor collector connected.
28*
VREF-OUT
CH1 reference voltage output. Outputs internal VREF (2.5 V:TYP) or external VREF.
29
VIN1
Pin for changeover between input AMP-A/internal VREF (TYP2.5 V) and input AMP-B/external VREF.
(VREF)-SW
30
VREF-IN
Reference voltage applied pin.
31
VIN4+
Input pin (+) for channel 4.
32
VIN4-
Input pin (-) for channel 4.
33
VIN4
Input pin for channel 4, input AMP output.
34
MUTE
All BTL AMP output ON/OFF.
35
VCONT
Loading output voltage setting.
36
S-GND
Signal system GND.
Port Name
Pin No.
Function
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
* Center frame (FR) becomes GND for the power system (P-GND). Set this to the minimum potential together with S-GND.
– 40 –
HT-CN400DVH/HT-CN400DVE/HT-CN500DVH/HT-CN500DVE
Figure 40 BLOCK DIAGRAM OF IC
FWD
Thermal Shutdown
Signal System GND
S-GND
VCONT
MUTE
VIN4
VIN4-
VIN4+
VREF-IN
VIN1(VREF)-SW
VREF-OUT(CH1)
RF
REG-OUT
REG-IN
VIN3+
VIN3-
VIN3
VIN2+
VIN2-
VIN2
VIN1+B
36
35
34
33
32
31
30
29
28
RF
27
26
25
24
23
22
21
20
19
UNit
Resistance:
Resistance:
Ω
MUTE
22k
VIN1/VREF-SW
Power System GND
5VREG (Extemal PNP)
22 k
11 k
22 k
11 k
22 k
11 k
11k
BTL-AMP Output
ON/OFF
(LOAD output voltage setting)
Input
Output Control
Level Shift
Level Shift
Level Shift
Level Shift
REV
VCC2
VLO-
VLO+
VO4+
VO4-
VO3+
VO3-
Power System GND
VO2+
VO2-
VO1+
VO1-
VCC1
AMP-A
AMP-B
VIN1
VIN1-A
VIN1+A
VIN1-B
RF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
FR
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
VIN1 (VREF)-SW
[L]: Internal VREF (2.5 V fixed)
[H]: Internal VREF
[L]: Internal VREF (2.5 V fixed)
[H]: Internal VREF
VIN1 (VREF)-SW
[L]: AMP-A
[H]: AMP-B
[L]: AMP-A
[H]: AMP-B
IC801 92LRCI6560-001: Motor Driver (LA6560)
– 41 –
HT-CN400DVH/HT-CN400DVE/HT-CN500DVH/HT-CN500DVE
IC003 92LRCI7272-002: (LC72720NM)
1
VREF
Output
Reference voltage output (VDDA/2).
2
MPXIN
Input
Baseband (multiplexed ) signal input.
3
VDDA
—
Analog system power supply (+5 V).
4
VSSA
—
Analog system ground.
5
FLOUT
Output
Subcarrier output (filter output).
6
CIN
Input
Subcarrier input (comparator input).
7
T1
Input
Test input (This pin must always be connected to ground.).
8
T2
Input
Test input (stand-by control).
0: Normal operation, 1: Stand-by state. (crystal oscillator stopped).
0: Normal operation, 1: Stand-by state. (crystal oscillator stopped).
9*
T3 (RDCL)
Input/Output* Test I/O (RDS clock output).
10*
T4 (RDDA)
Input/Output* Test I/O (RDS data output).
11*
T5 (RSFT)
Input/Output* Test I/O (Soft-decision control data output).
12
XOUT
Output
Crystal oscillator output (4.332/8.664 MHz).
13
XIN
Input
Crystal oscillator input. (external reference signal input).
14
VDDD
—
Digital system power supply (+5 V).
15
VSSD
—
Digital system ground.
16*
T6
Input/Output* Test I/O (Error status output, regenerated carrier output, error block count output).
(ERROR/57K/BE1)
17*
T7
Input/Output* Test I/O(Error correction status output, SK detection output, error block count output).
(CORREC/
ARI-ID/BE0)
ARI-ID/BE0)
18*
SYNC
Input/Output* Block synchronization detection output.
19*
RDS-ID
Output
RDS detection output.
20
DO
Output
Data output. Serial data interface (CCB).
21
CL
Input
Clock output. Serial data interface (CCB).
22
DI
Input
Data input. Serial data interface (CCB).
23
CE
Input
Chip enable. Serial data interface (CCB).
24
SYR
Input
Synchronization and RAM address reset (active high).
Port Name
Pin No.
Input/Output
Function
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Note: * Normally function as an output pin. Used as an I/O pin in test mode, which is not available to user applications.
VDDA
REFERENCE
VOLTAGE
ANTIALIASING
FILTER
CCB
TEST
VREF
FLOUT
CIN
57 kHz
BPF
(SCF)
SMOOTHING
FILTER
RAM
(24 BLOCK DATA)
ERROR CORRECTION
(SOFT DECISION)
CLK(4.332 MHz)
XIN
XOUT
OSC/DIVIDER
VREF
PLL
(57 kHz)
CLOCK
RECOVERY
(1187.5 Hz)
VDDD
VSSD
RDS-ID
SYNC
SYR
DATA
DECODER
SYNC/CE CONTROLLER
SYNC
DETECT-1
SYNC
DETECT-2
MEMORY
CONTROL
VSSA
MPXIN
DO
CL
DI
CE
T1
T2
T3~T7
+
–
Figure 41 BLOCK DIAGRAM OF IC
– 42 –
HT-CN400DVH/HT-CN400DVE/HT-CN500DVH/HT-CN500DVE
IC110 92LRCI8772-001: 6CH D/A 2CH A/D (WM8772)
1
MODE
Digital input
Control format selection.
0= Software control.
1= Hardware control.
0= Software control.
1= Hardware control.
2
MCK
Digital input
Master clock; 256, 384, 512 or 768 fs (fs= word clock frequency).
3
BCLK
Digital input/output
Audio interface bit clock.
4
LRC
Digital input/output
Audio left/right word clock.
5
DVDD
Supply
Digital positive supply.
6
DGND
Supply
Digital negative supply.
7
DIN1
Digital input
DAC channel 1 data input.
8
DIN2
Digital input
DAC channel 2 data input.
9
DIN3
Digital input
DAC channel 3 data input.
10
DOUT
Digital output
ADC data output.
11
ML/I2S
Digital input
Software Mode: Serial interface Latch signal.
Hardware Mode: Input Audio Data Format.
Hardware Mode: Input Audio Data Format.
12
MC/IWL
Digital input
Software Mode: Serial control interface clock.
Hardware Mode: Audio data input word length.
Hardware Mode: Audio data input word length.
13
MD/DM
Digital input
Software Mode: Serial interface data.
Hardware Mode: De-emphasis selection.
Hardware Mode: De-emphasis selection.
14*
MUTE
Digital input/output
DAC Zero Flag output or DAC mute input.
15
REFADC
Analogue output
ADC reference buffer decoupling pin; 10
µ
F external decoupling.
16
VREFN
Supply
ADC and DAC negative supply and substrate connection.
17
VREFP
Supply
DAC positive reference supply.
18
VMID
Analogue output
Midrail divider decoupling pin; 10
µ
F external decoupling.
19
AINR
Analogue input
ADC right input.
20
AINL
Analogue input
ADC left input.
21
VOUT1L
Analogue output
DAC channel 1 left output.
22
VOUT1R
Analogue output
DAC channel 1 right output.
23
VOUT2L
Analogue output
DAC channel 2 left output.
24
VOUT2R
Analogue output
DAC channel 2 right output.
25
VOUT3L
Analogue output
DAC channel 3 left output.
26
VOUT3R
Analogue output
DAC channel 3 right output.
27
AGND
Supply
Analogue negative supply and substrate connection.
28
AVDD
Supply
Analogue positive supply.
Port Name
Pin No.
Input/Output
Function
Note: Digital input pins have Schmitt trigger input buffers.
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
DACVREFN
VMID
DVDD
DGND
MUTE
MODE
ML/I2S
MC/IWL
MD/DM
DACVREFP
REFADC
ADCVREFN
ADCMCLK
DOUT
ADCLRC
DACLRC
ADCBCLK
AACBCLK
DIN1
DIN2
DIN3
DACMCLK
AVDD
AGND
VOUT1L
VOUT1R
VOUT2L
VOUT2R
VOUT3L
VOUT3R
STEREO
ADC
STEREO
DAC
LOW
PASS
FILTER
LOW
PASS
FILTER
LOW
PASS
FILTER
STEREO
DAC
STEREO
DAC
VREFN
VREFP
AUDIO
INTERFACE
&
DIGITAL
FILTERS
CONTROL INTERFACE
AINL
AINR
+
–
Figure 42 BLOCK DIAGRAM OF IC
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