Sharp HT-CN500DVH (serv.man3) Service Manual ▷ View online
– 51 –
HT-CN400DVH/HT-CN400DVE/HT-CN500DVH/HT-CN500DVE
134
HD10
Input/Output
Host data line 10.
AUX22
Input/Output
Aux2 data I/O 2.
SQSK
Input
Subcode-Q clock.
135
HD11
Input/Output
Host data line 11.
AUX23
Input/Output
Aux2 data I/O 3 when selected.
IRQ
Output
IRQ output.
136
HD12
Input/Output
Host data line 12.
AUX24
Input/Output
Aux2 data I/O 4 when selected.
C2PO
Input
C2PO error correction flag from CD-ROM.
137
HD13
Input/Output
Host data line 13.
AUX25
Input/Output
Aux2 data I/O 5 when selected.
SP
Input
16550 UART serial port input.
138
VSS
Input
Ground.
139
VCC
Input
Core power supply.
140
HD14
Input/Output
Host data line 14.
AUX26
Input/Output
Aux2 data I/O 6 when selected.
SQSI
Input
Subcode-Q sync.
141
HD15
Input/Output
Host data line 15.
AUX27
Input/Output
Aux2 data I/O 7 when selected.
IR
Input
IR remote control input.
142
HWRQ#
Output
Host write request.
DCI_REQ#
Output
DVD control interface request.
AUX41
Input/Output
Aux4 data I/O 1.
143
HRRQ#
Output
Host read request.
AUX40
Input/Output
Aux4 data I/O 0.
144
HIRQ
Input/Output
Host interrupt.
DCI_ERR#
Input/Output
DVD channel data error.
AUX47
Input/Output
Aux4 data I/O 7.
145
HRST#
Output
Host reset.
AUX35
Input/Output
Aux3 data I/O 5.
146
HIORDY
Input
Host I/O ready.
AUX33
Input/Output
Aux3 data I/O 3.
147
VSS
Input
Ground.
148
VEE
Input
I/O power supply.
149
HWR#
Input/Output
Host write.
DCI_CLK
Input/Output
DVD channel data clock.
AUX45
Input/Output
Aux4 data I/O 5.
150
HRD#
Output
Host read.
DCI_ACK#
Output
DVD channel data valid.
AUX46
Input/Output
Aux4 data I/O 6.
151
HIOSC16#
Input
Device 16-bit data transfer.
CAMCLK
Input
Camera port pixel clock input.
AUX34
Input/Output
Aux3 data I/O 4.
152
HCS1FX#
Output
Host select 1.
AUX37
Input/Output
Aux3 data I/O 7.
153
HCS3FX#
Output
Host select 3.
AUX36
Input/Output
Aux3 data I/O 6.
154
HA0
Input/Output
Host address bus.
AUX42
Aux4 data I/O 2.
155
HA1
Input/Output
Host address bus.
AUX43
Aux4 data I/O 3.
156
VSS
Input
Ground.
157
VEE
Input
I/O power supply.
158
HA2
Input/Output
Host address bus.
AUX44
Aux4 data I/O 4.
159
VEE
Input
I/O power supply.
160
AUX0
Input/Output
Auxiliary ports 0.
161
AUX1
Input/Output
Auxiliary ports 1.
162
AUX2
Input/Output
Auxiliary ports 2.
IOW#
Output
I/O write strobe.
IC106 92LRCI6028-001: Microcomputers (ES6028) (4/5)
Port Name
Pin No.
Input/Output
Function
– 52 –
HT-CN400DVH/HT-CN400DVE/HT-CN500DVH/HT-CN500DVE
IC106 92LRCI6028-001: Microcomputer (ES6028) (5/5)
Port Name
Pin No.
Input/Output
Function
163
VSS
Input
Ground.
164
VEE
Input
I/O power supply.
165
AUX3
Input/Output
Auxiliary ports 3.
IOR#
Output
I/O read strobe.
166
AUX4
Input/Output
Auxiliary ports 4.
167
AUX5
Input/Output
Auxiliary ports 5.
168
AUX6
Input/Output
Auxiliary ports 6.
169
AUX7
Input/Output
Auxiliary ports 7.
170
LOE#
Output
Device output enable.
171
VSS
Input
Ground.
172
VCC
Input
Core power supply.
173*
LCS0#
Output
Chip select 0.
174
LCS1#
Output
Chip select 1.
175
LCS2#
Output
Chip select 2.
176
LCS3#
Output
Chip select 3.
177
VSS
Input
Ground.
178-182
LD0-LD4
Input/Output
EPROM device data bus.
183
VEE
Input
I/O power supply.
184
VSS
Input
Ground.
185-191
LD5-LD11
Input/Output
EPROM device data bus.
192
VSS
Input
Ground.
193
VEE
Input
I/O power supply.
194-197
LD12-LD15
Input/Output
EPROM device data bus.
198
LWRLL#
Output
Device low-byte write enable.
199
LWRHL#
Output
Device high-byte write enable.
200
VSS
Input
Ground.
201
VEE
Input
I/O power supply.
202*
CAMIN0
Input
Camera YUV 0.
203*
CAMIN1
Input
Camera YUV 1.
204-207
LA0-LA3
Output
Device address output.
208
VSS
Input
Ground.
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
– 53 –
HT-CN400DVH/HT-CN400DVE/HT-CN500DVH/HT-CN500DVE
LA[21:0]
DSCK_EN
DSCK
DQM
DCS#[1:0]
DMA[11:0]
DWE#
DOE#
DRAS#[2:0]
DB[15:0]
DCAS#
DSCK
DQM
DCS#[1:0]
DMA[11:0]
DWE#
DOE#
DRAS#[2:0]
DB[15:0]
DCAS#
YUV[7:0]
PCLK2XSCN
PCLKQSCN
VSYNC#
HSYNC#
PCLK2XSCN
PCLKQSCN
VSYNC#
HSYNC#
CDAC
YDAC
UDAC
VDAC
YDAC
UDAC
VDAC
VREF
COMP
RSET
COMP
RSET
AUX[7:0]
RESET#
XIN
XOUT
RESET#
XIN
XOUT
LCS#[3:0]
LD[15:0]
LWRHL#
LWRLL#
LOE#
HA[2:0]
HD[15:0]
HWRQ#
HRDQ#
HRDQ#
HIRQ#
HRST#
HIORDY
HWR#
HRD#
HIOCS16#
HCS[1,3]FX#
DCI_ACL#
DCI_CLK
DCI_ERR#
DCI_REQ#
DCI_FDS#
TDMCLK
TDMDR
TDMDX
TDMFS
TDMTSC#
DCI[7:0]
RSD
RWS
RBCK
SPDIF
TBCK
MCLK
TSD[3:0]
TWS
Processor
Interface
SRAM
Interface
MPEG
Decoder
DRAM
Interface
2 k x 32 ROM
512 x 32 SRAM
Video
Processor
Video Output
On Screen
Display
Sub-Picture
Decoder
Video
Encoder
Clock
System
Demultiplexer
DVD
Descramble
Registers
ESS RISC
Processor
DMA
Controller
H0st/ATAPI/UDF
Loader Interface
Serial Audio
Interface
DCI Loader
Interface
TDM
Interface
Host/ATAPI
UDF
Interface
Serial
Audio
Audio
Interface
DCI
Interface
TDM
Interface
Screen
Display
DRAM
Clock,
Aux Ports
and Reset
VEE
HA2/AUX4[4]
VEE
AUX[0]
AUX[1]
AUX[1]
AUX[2]/IOW#
VSS
VEE
VEE
AUX[3]/IOR#
AUX[4]
AUX[5]
AUX[6]
AUX[7]
AUX[5]
AUX[6]
AUX[7]
LOE#
VSS
VCC
LCS0#
LCS1#
LCS2#
LCS3#
LCS1#
LCS2#
LCS3#
VSS
LD0
LD1
LD2
LD3
LD4
LD1
LD2
LD3
LD4
VEE
VSS
VSS
LD5
LD6
LD7
LD8
LD9
LD6
LD7
LD8
LD9
LD10
LD11
LD11
VSS
VEE
VEE
LD12
LD13
LD14
LD15
LD13
LD14
LD15
LWRLL#
LWRHL#
VSS
VEE
VEE
CAMIN0
CAMIN1
CAMIN1
LA0
LA1
LA2
LA3
LA1
LA2
LA3
VSS
VEE
LA4
LA5
LA6
LA7
LA8
LA9
VSS
VCC
LA10
LA11
LA12
LA13
LA14
LA15
LA16
VSS
VEE
LA17
LA18
LA19
LA20
LA21
RESET#
TDMDX/RSEL
VSS
VEE
TDMDR
TDMCLK
TDMFS
TDMTSC#
TWS/SEL_PLL2
TSD0/SEL_PLL0
VSS
VCC
TSD1/SEL_PLL1
TSD2
TSD3
MCLK
TBCK
SPDIF/PLL3
N.C.
VSS
VCC
RSD
RWS
RBCK
N.C.
XIN
XOUT
AVEE
VSS
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
VSS
HA1/AUX4[3]
HA0/AUX4[2]
HCS3FX#/AUX3[6]
HCS1FX#/AUX3[7]
HIOCS16#/CAMCLK/AUX3[4]
HRD#/DCI_ACK#/AUX4[6]
HWR#/DCI_CLK/AUX4[5]
VEE
VSS
HIORDY/AUX3[3]
HRST#/AUX3[5]
HIRO/DCI_ERR#/AUX4[7]
HRRO#/AUX4[0]
HWRQ#/DCI_REQ#/AUX4[1]
HD15/AUX2[7]/IR
HD14/AUX2[6]/SQSI
VCC
VSS
HD13/AUX2[5]/SP
HD12/AUX2[4]/C2PO
HD11/AUX2[3]//IRQ
HD10/AUX2[2]/SQSK
HD9/AUX2[1]/SQSO
HD8/DCI_FDS#/AUX2[0]/VFD_CLK
HD7/DCI7/AUX1[7]/VFD_DIN
VEE
VSS
HD6/DCI6/AUX1[6]/VFD_DOUT
HD5/DCI5/AUX1[5]
HD4/DCI4/AUX1[4]
HD3/DCI3/AUX1[3]
HD2/DCI2/AUX1[2]
HD1/DCI1/AUX1[1]
HD0/DCI0/AUX0[0]
VCC
VSS
HSYNC#/CAMIN7/AUX3[0]
VSYNC#/CAMIN6/AUX3[1]
PCLKQSCN/CAMIN5/AUX3[2]
PCLK2XSCN/CAMIN4
YUV7/CAMIN3
YUV6/VDAC
YUV5/YDAC
VSS
ADVEE
YUV4/RSET
YUV3/COMP
YUV2/CDAC
YUV1/VREF
YUV0/CAMIN2/UDAC
DCLK
VEE
VSS
DSCK
DQM
DSC0#
VEE
VSS
DCS1#
DB15
DB14
DB13
DB12
VEE
VSS
DB11
DB10
DB9
DB8
DB7
DB6
VSS
VCC
DB5
DB4
DB3
DB2
DB1
DB0
VSS
VEE
DMBS1
DMBS0
DRAS#
DWE#
DOE#/DSCK_EN
DCAS#
VEE
VSS
DMA11
DMA10
DMA9
DMA8
DMA7
DMA6
VSS
VEE
DMA5
DMA4
MDA3
DMA2
DMA1
DMA0
VSS
DSCK
DQM
DSC0#
VEE
VSS
DCS1#
DB15
DB14
DB13
DB12
VEE
VSS
DB11
DB10
DB9
DB8
DB7
DB6
VSS
VCC
DB5
DB4
DB3
DB2
DB1
DB0
VSS
VEE
DMBS1
DMBS0
DRAS#
DWE#
DOE#/DSCK_EN
DCAS#
VEE
VSS
DMA11
DMA10
DMA9
DMA8
DMA7
DMA6
VSS
VEE
DMA5
DMA4
MDA3
DMA2
DMA1
DMA0
104
103
102
101
100
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
IC106 92LRCI6028-001: Microcomputer (ES6028)
Figure 53 BLOCK DIAGRAM OF IC
– 54 –
HT-CN400DVH/HT-CN400DVE/HT-CN500DVH/HT-CN500DVE
FE
A/D Block
SLC Block
CLV/CAV Block
EFM Block
Frame sync protection
Frame sync insertion
EFM demodulation
CIRC Dec Block
CD-ROM Dec Block
DVD Dec Block
1Mbit DRAM
(LC78662NW ONLY)
AV Dec I/F Block
BCA Buff Block
SUBCODE I/F Block
DRAM I/F Block
Audio OUT Block
EFM PLL Block
JV Block
CLK GEN Block
CPU I/F Block
SYS PLL Block
CD Frame Sync
DVD Frame Sync
RF I/F Block
FC Counter
TR Counter
EV Counter
FG Counter
Defect
Servo Block
D/A Block
8bit
D/A
CMP
CMP
Servo DSP
(16x16+32 32)
MPX
8bit
A/D
A/D
FDO
TDO
SLDO
SPDO
SGC
TBAL
FBAL
BST
F0
TSTD0
TSTD1
TDO
SLDO
SPDO
SGC
TBAL
FBAL
BST
F0
TSTD0
TSTD1
TESIO
HFLIO
EMPH
DOUT
LRSY
ROMCK
ROMXA
C2F
LRSY
ROMCK
ROMXA
C2F
MD[15:0]
AVREQI
MA[10:0]
MRAS1B
MCASUB
MCASLB
MOEB
MWEB
MCASUB
MCASLB
MOEB
MWEB
AVACKO
AVDACK
AVSCTB
AVERRB
AVD[7:0]
AVSCTB
AVERRB
AVD[7:0]
FSX
EFLG
EFLG
(AD0)
(TEC)
(WO)
(RF_BH)
(BHC)
TE
RF_PH
RF_BH
RF_BH
JV
RREC
AD0
AD1
AD1
BHC
WO
TEC
FG
EVENT
RFP[3:0]
DEFECTI
DEFECTO
EFMP
XIN
XOUT
HWAITB
HIRQ0B
X16MIO
DVDCKIO
HDAT[7:0]
HADR[12:0]
HRDB
HWRB
HCSB
EFMN
SLCO1
SLCO2
SLCO2
SLCLPF0
SLCLPF1
SLCLPF1
PISET
FISET
LF1
LF2
LF3
LF2
LF3
PCN
PPDO
FPDO
VCOCTL
DVDFR
CDFR
PCK
JVAO
JVAIN
JVRVO
JVCPC
JVCPI
VPDO
VCOC
VRPFR
EFMOUT
IC803 92LRCI7866-001: DVD Front End (LC78663NRW)
Figure 54 BLOCK DIAGRAM OF IC
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