Sharp HT-CN500DVH (serv.man3) Service Manual ▷ View online
– 47 –
HT-CN400DVH/HT-CN400DVE/HT-CN500DVH/HT-CN500DVE
Port Name
Pin No.
Function
IC802 92LRCI09703-001: DVD Players RF Amp. (LA9703W) (2/2)
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
59
RFN
RF signal - input.
60*
N/C
N/C pin.
61
RFP
RF + signal.
62
CAO
Customer OP amplifier output pin.
63
VCC
Power pin (RF system).
64
CAN
Customer OP amplifier - input pin.
FM
S-METER
AM
S-METER
S-CURVE
SD
COMP
AM IF
AGC
ALC
BUFF
AM
OSC
REG
AM
MIX
AM
RF.AMP
DET
AM/FM
IF-BUFF
AM IF
FM
DET
TUNING
DRIVE
STEREO
DRIVE
3 rd 5 th
DECODER
ANTI-BIRDIE
P-DET
Ø
STEREO
SW
VCO
304kHz
FF
38 k
PILOT
DET
MUTE
FF
19k
GND
VCC
FF
19k
2
π
θ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Figure 47 BLOCK DIAGRAM OF IC
IC001 92LRCI1837-001: (LA1837)
– 48 –
HT-CN400DVH/HT-CN400DVE/HT-CN500DVH/HT-CN500DVE
IC106 92LRCI6028-001: Microcomputer (ES6028) (1/5)
1
VEE
Input
I/O power supply.
2-7
LA4-LA9
Output
Device address output.
8
VSS
Input
Ground.
9
VCC
Input
Core power supply.
10-16
LA10-LA16
Output
Device address output.
17
VSS
Input
Ground.
18
VEE
Input
I/O power supply.
19-22*,23* LA17-LA21
Output
Device address output.
24
RESET#
Input
Reset input, active low.
25
TDMDX
Output
TDM transmit data.
RSEL
Input
ROM Select.
26
VSS
Input
Ground.
27
VEE
Input
I/O power supply.
28
TDMDR
Input
TDM receive data.
29
TDMCLK
Input
TDM clock input.
30
TDMFS
Input
TDM frame sync.
31*
TDMTSC#
Output
TDM output enable.
32
TWS
Output
Audio transmit frame sync.
SEL_PLL2
Input
System and DSCK output clock frequency selection is made at the rising edge of RESET#.
The matrix below lists the available clock frequencies and their respective PLL bit settings.
The matrix below lists the available clock frequencies and their respective PLL bit settings.
33
TSD0
Output
Audio transmit serial data port 0.
SEL_PLL0
Input
Refer to the description and matrix for SEL_PLL2 pin 32.
34
VSS
Input
Ground.
35
VCC
Input
Core power supply.
36
TSD1
Output
Audio transmit serial data port 1.
SEL_PLL1
Input
Refer to the description and matrix for SEL_PLL2 pin 32.
37
TSD2
Output
Audio transmit serial data output 2.
38*
TSD3
Output
Audio transmit serial data output 3
39
MCLK
Input/Output
Audio master clock for audio DAC.
40
TBCK
Output
Audio transmit bit clock.
41
SPDIF
Output
S/PDIF output.
SEL_PLL3
Input
Clock source select.
42*
N.C.
No connect pins. Leave open.
43
VSS
Input
Ground.
44
VCC
Input
Core power supply.
45*
RSD
Input
Audio receive serial data.
46*
RWS
Input
Audio receive frame sync.
47*
RBCK
Input
Audio receive bit clock.
48*
N.C.
No connect pins. Leave open.
49
XIN
Input
Crystal input.
50
XOUT
Output
Crystal output.
51
AVEE
Input
Analog power for PLL.
52
VSS
Input
Ground.
53
DMA0
Output
DRAM address bus 0.
54
DMA1
Output
DRAM address bus 1.
55
DMA2
Output
DRAM address bus 2.
56
DMA3
Output
DRAM address bus 3.
57
DMA4
Output
DRAM address bus 4.
58
DMA5
Output
DRAM address bus 5.
59
VEE
Input
I/O power supply.
60
VSS
Input
Ground.
61
DMA6
Output
DRAM address bus 6.
62
DMA7
Output
DRAM address bus 7.
Port Name
Pin No.
Input/Output
Function
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
– 49 –
HT-CN400DVH/HT-CN400DVE/HT-CN500DVH/HT-CN500DVE
IC106 92LRCI6028-001: Microcomputer (ES6028) (2/5)
Port Name
Pin No.
Input/Output
Function
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
63
DMA8
Output
DRAM address bus 8.
64
DMA9
Output
DRAM address bus 9.
65
DMA10
Output
DRAM address bus 10.
66
DMA11
Output
DRAM address bus 11.
67
VSS
Input
Ground.
68
VEE
Input
I/O power supply.
69
DCAS#
Output
DRAM column address strobe.
70
DOE#
Output
DRAM output enable.
DSCL_EN
Output
DRAM clock enable.
71
DWE#
Output
DRAM write enable.
72
DRAS#
Output
DRAM row address strobe.
73
DMBS0
Output
SDRAM bank select 0.
74
DMBS1
Output
SDRAM bank select 1.
75
VEE
Input
I/O power supply.
76
VSS
Input
Ground.
77
DB0
Input/Output
DRAM data bus 0.
78
DB1
Input/Output
DRAM data bus 1.
79
DB2
Input/Output
DRAM data bus 2.
80
DB3
Input/Output
DRAM data bus 3.
81
DB4
Input/Output
DRAM data bus 4.
82
DB5
Input/Output
DRAM data bus 5.
83
VCC
Input
Core power supply.
84
VSS
Input
Ground.
85
DB6
Input/Output
DRAM data bus 6.
86
DB7
Input/Output
DRAM data bus 7.
87
DB8
Input/Output
DRAM data bus 8.
88
DB9
Input/Output
DRAM data bus 9.
89
DB10
Input/Output
DRAM data bus 10.
90
DB11
Input/Output
DRAM data bus 11.
91
VSS
Input
Ground.
92
VEE
Input
I/O power supply.
93
DB12
Input/Output
DRAM data bus 12.
94
DB13
Input/Output
DRAM data bus 13.
95
DB14
Input/Output
DRAM data bus 14.
96
DB15
Input/Output
DRAM data bus 15.
97*
DCS1#
Output
SDRAM chip select 1.
98
VSS
Input
Ground.
99
VEE
Input
I/O power supply.
100
DCS0#
Output
SDRAM chip select 0.
101
DQM
Output
Data input/output mask.
102
DSCK
Output
Output clock to SDRAM.
103
VSS
Input
Ground.
104
VEE
Input
I/O power supply.
105
DCLK
Input
27 MHz clock input to PLL.
106
YUV0
Output
YUV0 pixel output data.
CAMIN2
Input
Camera input 2.
UDAC
Output
Video DAC output.
Y: Luma component for YUV and Y/C processing.
C: Chrominance signal for Y/C processing
U: Chrominance component signal for YUV mode.
V: Chrominance component signal for YUV mode.
Y: Luma component for YUV and Y/C processing.
C: Chrominance signal for Y/C processing
U: Chrominance component signal for YUV mode.
V: Chrominance component signal for YUV mode.
107
YUV1
Output
YUV1 pixel output data.
VREF
Input
Internal voltage reference to video DAC. Bypass to ground with 0.1
µ
F capacitor.
– 50 –
HT-CN400DVH/HT-CN400DVE/HT-CN500DVH/HT-CN500DVE
IC106 92LRCI6028-001: Microcomputers (ES6028) (3/5)
Port Name
Pin No.
Input/Output
Function
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
108
YUV2
Output
YUV2 pixel output data.
CDAC
output
Video DAC output. Refer to description and matrix for UDAC pin 106.
109
YUV3
Output
YUV3 pixel output data.
COMP
Input
Compensation input. Bypass to ADVEE with 0.1
µ
F capacitor.
110
YUV4
Output
YUV4 pixel output data.
RSET
Input
DAC current adjustment resistor input.
111
ADVEE
Input
Analog power for video DAC.
112*
VSS
Input
Ground.
113
YUV5
Output
YUV5 pixel output data.
YDAC
Output
Video DAC output. Refer to description and matrix for UDAC pin 106.
114
YUV6
Output
YUV6 pixel output data.
VDAC
Output
Video DAC output. Refer to description and matrix for UDAC pin 106.
115*
YUV7
Output
YUV7 pixel output data.
CAMIN3
Input
Camera YUV 3.
116*
PCLK2XSCN
Input/Output
27 MHz video output pixel clock.
CAMIN4
Input
Camera YUV 4.
117
PCLKQSCN
Output
13.5 MHz video output pixel clock.
CAMIN5
Input
Camera YUV 5.
118
VSYNC#
Input/Output
Vertical sync, active low.
CAMIN6
Input
Camera YUV 6.
119
HSYNC#
Input/Output
Horizontal sync, active low.
CAMIN7
Input
Camera YUV 7.
120
VSS
Input
Ground.
121
VCC
Input
Core power supply.
122
HD0
Input/Output
Host data I/O 0.
DCI0
Input/Output
DVD channel data I/O 0.
AUX10
Input/Output
Aux1 data I/O 0.
123
HD1
Input/Output
Host data I/O 1.
DCI1
Input/Output
DVD channel data I/O 1.
AUX11
Input/Output
Aux1 data I/O 1.
124
HD2
Input/Output
Host data I/O 2.
DCI2
Input/Output
DVD channel data I/O 2.
AUX12
Input/Output
Aux1 data I/O 2.
125
HD3
Input/Output
Host data I/O 3.
DCI3
Input/Output
DVD channel data I/O 3.
AUX13
Input/Output
Aux1 data I/O 3.
126
HD4
Input/Output
Host data I/O 4.
DCI4
Input/Output
DVD channel data I/O 4.
AUX14
Input/Output
Aux1 data I/O 4.
127
HD5
Input/Output
Host data I/O 5.
DCI5
Input/Output
DVD channel data I/O 5.
AUX15
Input/Output
Aux1 data I/O 5.
128
HD6
Input/Output
Host data I/O 6.
DCI6
Input/Output
DVD channel data I/O 6.
DCI6
Input/Output
DVD channel data I/O 6.
AUX16
Input/Output
Aux1 data I/O 6.
VFD_DOUT
Input
VFD data output.
129
VSS
Input
Ground.
130
VEE
Input
I/O power supply.
131
HD7
Input/Output
Host data I/O 7.
DCI7
Input/Output
DVD channel data I/O 7.
AUX17
Input/Output
Aux1 data I/O 7.
VFD_DIN
Input
VFD data input.
132
HD8
Input/Output
Host data bus 8.
DCI_FDS#
Input/Output
DVD input sector start.
AUX20
Input/Output
Aux2 data I/O 0.
VFD_CLK
Input
VFD clock input.
133
HD9
Input/Output
Host data line 9.
AUX21
Input/Output
Aux2 data I/O 1.
SQSQ
Input
Subcode-Q data.
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