Sharp DX-SX1 (serv.man2) Service Manual ▷ View online
DX-SX1H
– 61 –
IC805 RH-iX1539GEZZ: Flash ROM (IX1539GE) (2/2)
Pin No. Terminal Name Input/Output
Function
42
DQ6
Input/Output
Lower byte data input/output: Data and command input during cycle of writing command user
interface. Memory array, identifier, and status data output when reading various data.
Float condition in case of chip non-select or output disable.
interface. Memory array, identifier, and status data output when reading various data.
Float condition in case of chip non-select or output disable.
43
DQ14
Input/Output
Upper byte data input/output: The function is the same as shown in case of the lower byte data
input/output above. Operating only in x16 mode. Floating in x 8 mode. DQ15/A-1: address
input/output above. Operating only in x16 mode. Floating in x 8 mode. DQ15/A-1: address
44
DQ7
Input/Output
Lower byte data input/output: Data and command input during cycle of writing command user
interface. Memory array, identifier, and status data output when reading various data.
Float condition in case of chip non-select or output disable.
interface. Memory array, identifier, and status data output when reading various data.
Float condition in case of chip non-select or output disable.
45
DQ15
Input/Output
Upper byte data input/output: The function is the same as shown in case of the lower byte data
input/output above. Operating only in x16 mode. Floating in x 8 mode. DQ15/A-1: address
input/output above. Operating only in x16 mode. Floating in x 8 mode. DQ15/A-1: address
46
GND
—
Ground
47
NC
—
Not used
48
A16
Input
Block select addresses: Select 1/32 erase block. These addresses are latched during data entry,
erase and lock block.
erase and lock block.
ID
REGISTOR
CSR
ESRs
DQ8-15
DQ0-7
INPUT/
OUTPUT
LOGIC
REGISTOR
BYTE#
CUI
WSM
16-KBYTE
BLOCK 31
16-KBYTE
BLOCK 30
16-KBYTE
BLOCK 1
16-KBYTE
BLOCK 0
CE#
OE#
WE#
RP#
RY/BY#
VPP
VCC
GND
Y GATE/DETECTION
Y-
DECODER
X-
DECODER
A1-17
OUTPUT
BUFFER
OUTPUT
BUFFER
INPUT
BUFFER
INPUT
BUFFER
INPUT
BUFFER
DATA QUEUE
REGISTOR
OUTPUT MULTIPLEXER
DATA
COMPARATOR
ADDRESS
QUEUE LATCH
ADDRESS COUNTER
PROGRAM
ERASE
VOLTAGE
SWITCH
Figure 61 BLOCK DIAGRAM OF IC
DX-SX1H
– 62 –
IC901 VHiCXD2751Q-1: SACD Playback Signal Processor (CXD2751Q) (1/2)
1
XSRQ
Output
Output terminal for data request to be input in the front end processor.
2
XSHD
Input
Input terminal for header flag to be output from the front end processor.
3
VDD
—
Power supply terminal, +3.3V
4
VSS
—
Ground terminal
5
SDCK
Input
Input terminal for data transmitting clock to be output from the front end processor
6
SMUTE
Input
Soft mute terminal
H: Soft mute of audio output, L: Released
H: Soft mute of audio output, L: Released
7
XMSLAT
Input
Latch input terminal for microcomputer serial communication
Latches addresses and data when this terminal rises.
Latches addresses and data when this terminal rises.
8
MSCK
Input
Shift clock input terminal for microcomputer serial communication
Inputs and shifts the serial input data when the clock to be input in this terminal rises.
Read-out data change when the clock to be input in this terminal falls.
Inputs and shifts the serial input data when the clock to be input in this terminal rises.
Read-out data change when the clock to be input in this terminal falls.
9
MSDATI
Input
Data input terminal for microcomputer serial communication (Microcomputer -> CXD2751Q)
Inputs serial data and addresses for communication.
Inputs serial data and addresses for communication.
10
MSDATO
Output
Data input terminal for microcomputer serial communication (CXD2751Q -> Microcomputer)
High impedance except during output
High impedance except during output
11
MSREDY
Output
Ready-to-output flag for microcomputer serial communication. Outputs "L", if complete.
Open drain.
Open drain.
12*
XMSDOE
Output
Data enable terminal for microcomputer serial communication
Makes this terminal active when using the try state buffer outside.
Makes this terminal active when using the try state buffer outside.
13
XRST
Input
Resets entire IC when reset terminal is "L".
Clock which is output from output terminals EXCKO1, EXCKO2, and LRCK does not stop during reset.
Clock which is output from output terminals EXCKO1, EXCKO2, and LRCK does not stop during reset.
14
MCKI
Input
Master clock input terminal
Inputs clock of 512Fs (22.579 MHz) or 768Fs (33.869 MHz).
Inputs clock of 512Fs (22.579 MHz) or 768Fs (33.869 MHz).
15
VSS
—
Ground terminal
16
CK75S
Input
Master clock select terminal. Selects "H" in case of 768Fs and "L" in case of 512Fs.
17
EXCKO1
Output
External output clock terminal 1. Outputs 768Fs/512Fs/256Fs/128Fs according to setting.
18*
EXCKO2
Output
External output clock terminal 2. Outputs 768Fs/512Fs/256Fs/128Fs according to setting.
19*
LRCK
Input/Output
IFs (44.1kHz) clock input/output terminal. Selects master/slave according to setting.
20*
NC
—
Not used
21*
MNT2
Output
Monitor output terminal. Outputs partial internal operation according to setting.
22
TRST
Input
Reset terminal for test. Inputs power-on reset signal or fixed at "L".
23
TCK
Input
Test clock input terminal. Fixed at "L".
24*
TDI
Input
Test input terminal. Open
25*
TENA1
Input
Test input terminal. Open
26*
TDO
Output
Test input terminal. Open
27
VST
—
Test ground terminal. Connected to ground
28
VDD
—
Power supply terminal, +3.3V
29
VSS
—
Ground terminal
30*, 31* MNT1, MNT0
Output
Monitor output terminal. Outputs partial internal operation according to setting.
32*
XBIT
Output
DST related monitor terminal. Not connected.
33*
F75HZ
Output
75Hz clock output terminal
34*
SUPDAT
Output
Supplementary data serial output terminal
35*
XSUPAK
Output
Supplementary data effective flag terminal
Outputs "L" when supplementary data are effective.
Outputs "L" when supplementary data are effective.
36*
SUPEN
Output
Supplementary data byte-unit enable output terminal
Changes to "H" at the break of 1 byte (8 bits) of serial data.
Changes to "H" at the break of 1 byte (8 bits) of serial data.
37
TEST1
Input
Test input terminal. Fixed at "L".
38
VSS
—
Ground terminal
39
TEST2
Input
Test input terminal. Fixed at "L".
40, 41
VSS
—
Ground terminal
42*
BCKD
Input/Output
Phase reference signal input/output terminal for DSD data phase modulation output
Input/output according to setting
Input/output according to setting
43*-45*
NC
—
Not used
Pin No. Terminal Name Input/Output
Function
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
DX-SX1H
– 63 –
IC901 VHiCXD2751Q-1: SACD Playback Signal Processor (CXD2751Q) (2/2)
46
BCKA
Input/Output
Shift clock input/output terminal for DSD data output. Input/output according to setting.
47
DSAL
Output
Lch-DSD data output terminal. Phase modulation output according to setting.
48
DSAR
Output
Rch-DSD data output terminal. Phase modulation output according to setting.
49
ZDFLGL
Output
Lch zero data detection flag. "H": when silent data continue for 300msec.
50
ZDFLGR
Output
Rch zero data detection flag. "H": when silent data continue for 300msec.
51
A0
Output
DRAM address output terminal (LSB)
52
A1
Output
DRAM address output terminal
53
VDD
—
Power supply terminal, +3.3V
54
VSS
—
Ground terminal
55-62
A2-A9
Output
DRAM address output terminal
63
A10
Output
DRAM address output terminal (MSB)
64*
NC
—
Not used
65
VSS
—
Ground terminal
66
XWE
Output
DRAM write enable output terminal. Connected to WE terminal of DRAM.
67
XCAS
Output
DRAM column address strobe output terminal. Connected to CAS terminal of DRAM.
68
XRAS
Output
DRAM row address strobe output terminal. Connected RAS terminal of DRAM.
69
XOE
Output
DRAM read enable output terminal. Connected OE terminal of DRAM.
70-77
DQ0-DQ7
Input/Output
DRAM data input/output terminal
78
VDD
—
Power supply terminal, +3.3V
79
VSS
—
Ground terminal
80
WCK
Input
Operation clock for detecting PSP physical disc mark. Inputs 27.00MHz.
81
WRFD
Input
RF data input terminal for detecting PSP physical disc mark
Inputs RF data made binary by slicer.
Inputs RF data made binary by slicer.
82
WAD0
Input
A/D data input/output terminal for detecting PSP physical disc mark (LSB)
83-88
WAD1-WAD6
Input
A/D data input/output terminal for detecting PSP physical disc mark
89
WAD7
Input
A/D data input/output terminal for detecting PSP physical disc mark (MSB)
90
VSS
—
Ground terminal
91
SD7
Input
Input terminal for stream data to be output from the front end processor (MSB)
92-97
SD6-SD1
Input
Input terminal for stream data to be output from the front end processor
98
SD0
Input
Input terminal for stream data to be output from the front end processor (LSB)
99
SDEF
Input
Input terminal for error flag to be output from the front end processor
100
XSAK
Input
Input terminal for data effective flag to be output from the front end processor
Pin No. Terminal Name Input/Output
Function
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
1
99
91 ~ 98
89 ~ 82
5
2
81
80
11
7
8
9
10 13
14 16 17 18 19
6
42
48
47
46
50
49
33
36
35
34
69
66
67
68
77 ~ 70
100
63~55,
52, 51
PSP
CPU-I/F
DSD
I/F
SUP-I/F
FADE-
INPUT/OUTPUT
XSRQ
SDEF
SD[7:0]
WAD[7:0]
SDCK
XSAK
XSHD
WRFD
WCK
MSREDY
XMSLAT
MSCK
MSDATI
MSDATO
XRST
MCKI
CK75S
EXCKO1
EXCKO2
LRCK
SMUTE
BCKA
DSAL
DSAR
BCKD
SUPDAT
XSUPAK
SUPEN
F75HZ
A[10:0]
XRAS
XCAS
XWE
XOE
DQ[7:0]
DECRYPTION
STREAM MANAGER
DIRECT STREAM
TRANSFER DECODER
TIMING
Figure 63 BLOCK DIAGRAM OF IC
DX-SX1H
– 64 –
IC902 VHiADC08351-1: A/D Converter (ADC08351)
1
OE
CMOS/TTL compatible digital input terminal.
When this terminal is set to Low, digital output of ADC08351 becomes enable.
When this terminal is set to High, digital output changes to the high-impedance condition.
When this terminal is set to Low, digital output of ADC08351 becomes enable.
When this terminal is set to High, digital output changes to the high-impedance condition.
2
DGND
Ground return circuit terminal for digital power supply.
3-10
D0-D7
Conversion data output terminal. C0 shows LSB, and D7 shows MBS.
Effective data are output on data bus immediately after CLK input rising edge.
When OE terminal is set to Low, these terminals become enable.
Effective data are output on data bus immediately after CLK input rising edge.
When OE terminal is set to Low, these terminals become enable.
11
VD
Positive digital power voltage terminal. Connected to +3V power supply.
VA and VD are supplied from the common power supply.
VA and VD are supplied from the common power supply.
12
CLK
CMOS/TTL compatible clock input terminal. VIN is sampled at CLK input trailing edge.
13
VD
Positive digital power voltage terminal. Connected to +3V voltage power.
14
VREF
Positive reference voltage input terminal. Voltage of this terminal ranges from 0.75V to VA.
15
PD
CMOS/TTL compatible digital input terminal.
When this terminal is set to High, ADC08351 enters the power down mode, minimizing power consumption.
When this is set to Low, the device enters the normal operation mode.
When this terminal is set to High, ADC08351 enters the power down mode, minimizing power consumption.
When this is set to Low, the device enters the normal operation mode.
16
VA
Positive analog power voltage terminal: To connect +3V voltage power.
17
VIN
Analog signal input. Convertible input ranges from 0.5Vp-p to 0.68Va.
18, 19
AGND
Ground return circuit terminal for analog power supply.
20
DGND
Ground return circuit terminal for digital power supply.
Pin No.
Terminal Name
Function
V
REF
V
IN
AGND
MUX
12k
18k
266
26
256
CLK
PD
AGND DGND
OE
DATA
OUT
(D0~D7)
8
17
17
17
8
8
8
1
99
V
D
+
V
A
+
SWITCH
ROUGH/FINE
COMPARATOR
ROUGH/FINE
COMPARATOR
Encoder and error correction
ENCODER
AND
ERROR
CORRECTION
ENCODER
AND
ERROR
CORRECTION
OUTPUT
DRIVER
CLOCK
GENERATOR
14
17
18
12
15
19
2,20
1
3
10
~
13,11
16
Figure 64 BLOCK DIAGRAM OF IC
Click on the first or last page to see other DX-SX1 (serv.man2) service manuals if exist.